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| 05:51 | Bertl_oO | off to bed now ... have a good one everyone!
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| 14:20 | Bertl | morning folks!
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| 15:20 | eppisai | I had set the axiom remote visualizer on virtual serial port /dev/pts/1 and then started the visualiser using command "./AXIOM_Remote_Firmware_Visualiser -p /dev/pts/4" . It open GUI of the axiom remote. But when i click "Compile&flash" button on vs code, it gave me an error "pic32prog: command not found" . I had aquired the binary of pic32prog
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| 15:20 | eppisai | but on running it is saying not "No target found".
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| 15:22 | eppisai | if anyone can tell me where i am going wrong or what should i do further to setup the axiom remote, then it will be very helpful
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| 15:22 | BAndiT1983 | hi eppisai
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| 15:22 | BAndiT1983 | the serial port feature is not implemented fully yet and was only added while developing a prototype
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| 15:23 | BAndiT1983 | compile&flash will only work for the real board
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| 15:23 | BAndiT1983 | as the visualiser is using most parts of real firmware, it's already sufficient to modify the UI and implement the logic
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| 15:36 | eppisai | oh. So, to implement T1193 (checkbox GUI element) I should only look into "AXIOM_Remote_Firmware_Visualizer"?
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| 15:37 | metal_dent[m] | yes, you won't require the serial ports for the GUI task
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| 15:38 | eppisai | Ok,thank you!=D
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| 15:39 | BAndiT1983 | eppisai: in fact, you have to look into the firmware, like i said, the visualiser is using the firmware to replicate as most parts of the real thing as possible
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| 15:42 | eppisai | ohk...
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| 15:43 | eppisai | thanks!
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| 17:22 | EmilJ | hi anuejn and vup once again! I'm trying to simulate my design, but I'm not sure how to work with the SimPlatform setup. I can see there's some deep idiomatic Python stuff going on with sim.py and can't really parse it in my head. What would be the minimal usage? Or should I write it first as a generic nmigen simulation? I sort of got stuck on that because the sim accepts exactly one module, and I had to instantiate an ImageStream as a submodule to construc
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| 17:22 | EmilJ | https://gitlab.com/tywonemi-school-stuff/zynq-hdmi-nmigen/-/blob/master/axi_burster_test.py
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| 17:24 | vup | EmilJ: your last message cut off after "construc"
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| 17:27 | vup | so in general Streams are not Modules, they contain no logic, they are "just" a convenient way to bundle some signals together
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| 17:28 | vup | so the module you are simulating here is just the AxiBurster, you then can drive the ImageStream from the simulation and look at what the AxiBurster does to it
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| 17:28 | vup | furthermore in the nmigen-gateware repo there are a lot of examples for the SimPlatform: for instance take a look at this: https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/hdmi/hdmi_test.py
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| 17:28 | Bertl | off for now ... bbl
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| 17:29 | Bertl | changed nick to: Bertl_oO
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| 17:29 | vup | or maybe look at this for a simulation working with AXI: https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/bus/axi/buffer_writer_test.py
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| 17:38 | EmilJ | ah, that's weird. Does IRC or this server have a message length limit? the last thing I wrote was "construct my AxiBurster."
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| 17:38 | EmilJ | I did look at the other test files and created a minimal example which should behave the same way
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| 17:39 | EmilJ | did the gitlab link send? I'm starting to distrust Convos...
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| 17:40 | vup | yes the gitlab link came through
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| 17:40 | vup | and yes IRC has a message length limit
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| 17:41 | vup | usually IRC clients automatically split a message that is too long into multiple though
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| 17:43 | vup | EmilJ: so you probably want two processes, one that send stuff into the ImageStream and one that looks at what the AxiBurster spews out
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| 17:43 | EmilJ | Well, for now I'd like to get simulate it as it is, even if everything stays in reset - I'll feed data into it once I have that working
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| 17:44 | EmilJ | does the UnitTest setup assume things about the location of the testing script? How are unit tests invoked in command line?
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| 17:45 | EmilJ | Right now, just running the script gets me AssertionError on line 30 in sim.py
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| 17:45 | vup | `python3 -m pytest src/` is what we use for the tests
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| 17:47 | EmilJ | Ah, thanks
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| 18:15 | EmilJ | Hm, stumped again, my call to platform.sim() fails on elaboration in the prepare function: https://0bin.net/paste/55zDJvNJ#OvIAai-1c3GiMPvDxtkFxtDz51/5BRB3zfyA1kn6vog
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| 18:19 | vup | EmilJ: elaborate gets self and the platform
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| 18:19 | vup | your AxiBurster elaborate only takes self
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| 18:20 | EmilJ | I see, thank you
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