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#apertus IRC Channel Logs

2019/08/06

Timezone: UTC


00:24
Bertl_oO
off to bed now ... have a good one everyone!
00:24
Bertl_oO
changed nick to: Bertl_zZ
00:57
apurvanandan[m]
Anybody available who has access to beta?
01:58
aSobhy
I'm
01:58
apurvanandan[m]
I meant root access :)
01:58
apurvanandan[m]
to ZBox
01:59
aSobhy
ah okay not me xD
02:00
apurvanandan[m]
How is it going?
02:02
aSobhy
I'm reading the files that on beta_e and getting lost
02:03
aSobhy
pm
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05:06
BAndiT1983|away
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BAndiT1983
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12:46
Bertl_zZ
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12:46
Bertl
morning folks!
12:46
apurvanandan[m]
Good morning Bertl!
14:20
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16:10
BAndiT1983|away
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16:37
Bertl
apurvanandan[m], aSobhy: good news, I wrote a bit file loader for the Beta which can load the MachXO2 SRAM much much faster
16:40
Bertl
for what pic_jtag_load.py takes about 10 seconds to program, now pic_jtag_bitload.py does in about 1 second
16:41
Bertl
and you do not need to mess around with the svf files, just generate an SRAM .bit file
16:56
aSobhy
ah thats a good news really
16:56
aSobhy
:D
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18:04
Bertl
aSobhy, apurvanandan[m]: here is a small example how to use the JTAG ER1 to read out registers on the MachXO2
18:05
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/jtagreg/
18:18
aSobhy
what I have done Is: add the jtagf module and the TDO will be multiplexed with the BER count shift register and the enable of shifting will be JRTI1 that corresponds to ER1
18:18
aSobhy
Is that right ?
18:18
Bertl
check the example code
18:19
aSobhy
OK
18:32
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/jtagreg/pic_jtag_er1.py is an example how to exchange data
18:47
apurvanandan[m]
Bertl, Can I copy the contents on 1x USB 3.0 Plugin Module wiki page to Gearwork for USB 3.0 Plugin Module wiki page, as I think different wiki page aren't required for it
18:48
Bertl
not sure what you want to do, but be careful when moving data around, especially if there are links to those pages
18:48
Bertl
when in doubt, double check with se6ast1an or RexOrMatrix[m]
18:48
apurvanandan[m]
Ok definitely :)
18:49
apurvanandan[m]
aSobhy, I am going to use beta, is it free?
18:50
se6ast1an
Please don't create content duplets
18:50
se6ast1an
Best link to existing content
18:50
apurvanandan[m]
Ok understood it :) se6ast1an
18:51
se6ast1an
Your page should contain stuff about your work, in the explanation you can of course link to other relevant pages like the hardware page of the plugin module
18:52
apurvanandan[m]
Got it :)
18:56
apurvanandan[m]
Can we use pic_jtag_bitload.py for programming the USB module also?
18:56
aSobhy
It is free now :) apurvanandan[m]
18:57
apurvanandan[m]
Thanks aSobhy
18:57
apurvanandan[m]
Bertl using the same pass code
18:57
Bertl
apurvanandan[m]: in theory yes, but it requires the bridge via the RFW
18:58
apurvanandan[m]
Yeah using the pass through code on RFW?
18:58
Bertl
yup
18:58
apurvanandan[m]
great!
18:59
aSobhy
Thanks Bertl thats save alot of time :)
19:00
apurvanandan[m]
aSobhy: Everytime I program my hardware my 4 minutes are lost, excluding compilation time
19:02
aSobhy
Actuallt I meant for the .py file
19:02
apurvanandan[m]
oh, okay
19:03
apurvanandan[m]
Bertl: I tried what you suggested ie send 3 out of 4 data at ft601_clk
19:03
apurvanandan[m]
No different
19:03
Bertl
where 'no different' means?
19:03
apurvanandan[m]
Same issue there also, values are lost by this method also
19:04
apurvanandan[m]
Exactly same problem like previous method
19:04
Bertl
whatever 'previous method' was :)
19:05
Bertl
it would be a perfect time to create a wiki page with the information what was tested (including setup, etc) and what problems were found
19:08
apurvanandan[m]
And on counting the number of values lost they were around some thousands of 32 bit values
19:08
apurvanandan[m]
Sorry, let me explain in detail
19:08
apurvanandan[m]
I had this problem of data being skipped due to FIFO getting full at some times
19:08
apurvanandan[m]
I diagnosed that by putting at disable/pause condition on counter when FIFO is full and made write enable also zero at FIFO full condition
19:09
apurvanandan[m]
You suggested me to clock the FIFO with FT601CLK but give 75
19:09
apurvanandan[m]
but give only 75% of data
19:10
apurvanandan[m]
This way get the similar setup but with synchronous clock
19:10
Bertl
did you check if the FIFO slowly gets full or stays basically empty till point X where the controller stalls and the FIFO runs full?
19:11
apurvanandan[m]
I tried this thing and found out that the results are same as earlier
19:12
apurvanandan[m]
Okay forgot to check, checking that now
19:23
apurvanandan[m]
So after 187 million clock of FIFO being not full, the fifo gets full for 1000 clocks
19:23
apurvanandan[m]
These numbers vary a little
19:23
Bertl
you want to check almost empty and almost full with e.g. 30%/70% of the FIFO
19:24
Bertl
otherwise you don't know if it gets slowly full or suddenly
19:25
Bertl
best add all four singals to your output, i.e. empty, almost empty, almost full and full
19:26
Bertl
(note that full is unlikely to end up in the FIFO :)
19:27
apurvanandan[m]
Okay, that will take a little time ( need to regenerate fifo with 30 and 70 thresholds)
19:28
Bertl
regenerate?
19:28
apurvanandan[m]
By IPexpress and then make modifications that I made earler
19:29
Bertl
still using IPexpress ...
19:29
Bertl
well, it's your time ;-)
19:30
apurvanandan[m]
What do I say now :/
19:31
Bertl
note that you can set pmi_full_flag to something below the FIFO depth
19:31
Bertl
which should actually allow you to record 'full' in the FIFO
19:33
apurvanandan[m]
okay , i see
19:34
apurvanandan[m]
Bertl, please tell possible reasons for both slowly filling and abruptly filling. I will debug for both reasons
19:35
Bertl
well, if the controller cannot catch up, it will fill slowly, if the controller works just fine till it suddenly stalls (retransmit, whatever) it will happen abruptly
19:42
apurvanandan[m]
Okay, I have something to say here. I removed some 80 lines of useless code in the controller https://gist.github.com/apurvanandan1997/27a217c0cdc40d92343d748850d38837 and it doesn't retransmit at all instead when the fifo gets empty or the fifo inside ft601 gets full, it save 3 values taken out of the fifo for future transmission due to difference in timing of FT601_TXE_N and FT601_WR_N
19:43
apurvanandan[m]
https://ibb.co/r5DD2Zf
19:44
apurvanandan[m]
In 245 Synchronous FIFO mode master read operation, the bus master shall be able to read out the maximum possible data in the RX FIFO in one read transaction, i.e. the bus master shall be able to read out 4 KB in one bus transaction. In write operations, if the bus master expects the data to be transferred on the USB bus in a maximum possible packet length, it should write the
19:44
apurvanandan[m]
data to the FIFO in a single bus transaction.
19:45
Bertl
doesn't matter much (i.e. it's now 'whatever' instead of 'retransmit, whatever')
19:46
apurvanandan[m]
Okay :P
20:31
BAndiT1983
changed nick to: BAndiT1983|away
21:57
apurvanandan[m]
Bertl, I have the statistics now
21:57
Bertl
excellent, let's see
21:57
aSobhy
Bertl: I'm confused with that example http://vserver.13thfloor.at/Stuff/AXIOM/BETA/jtagreg/jtagreg.vhd
21:57
aSobhy
why at the JTAGF_inst (TCK, TMS, TDI) are set to zero
21:58
apurvanandan[m]
Fifo is most of the time getting empty after sending 14 values
21:58
aSobhy
and from the document JTCK is drived from TCK
21:58
Bertl
aSobhy: because this is an access port to the MachXO2 JTAG which you do not want to mess with
21:58
se6ast1an
off to bed
21:58
se6ast1an
good night
21:59
Bertl
nn
21:59
apurvanandan[m]
Fifo seems to be always amlost empty , except before it gets completely full
21:59
Bertl
aSobhy: the J* ports are only active for the ER1 instruction, and that's where you want to hook into
22:00
Bertl
the TCK/TMS/TDI/TDO is a JTAG access port to the MachXO2 JTAG bus
22:01
apurvanandan[m]
It gets completely full after some 7-10 thousand
22:01
apurvanandan[m]
It gets almost full and immediately get full and thousand values are lost
22:01
apurvanandan[m]
Most of time it is almost empty
22:01
apurvanandan[m]
and switches between empty and non empty after approx 14 values
22:01
apurvanandan[m]
Anything else you would like to know?
22:02
aSobhy
so how I'll set them to 0 ? or connecting them(TCK/TMS/TDI/TD) to the PIC16
22:02
apurvanandan[m]
So it seems there are abrupt pauses
22:03
Bertl
almost empty is set to about 30% that would be 150 words or so?
22:03
apurvanandan[m]
158 words
22:03
apurvanandan
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22:04
Bertl
how does a backlog of 158+ words arise?
22:04
apurvanandan
exit
22:04
apurvanandan
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22:04
apurvanandan[m]
I don't know exactly how does that happen
22:04
Bertl
aSobhy: you just ignore the access port TCK/TMS/TDI/TDO
22:05
Bertl
apurvanandan[m]: well, as previously suggested, I'd get rid of the controller
22:05
Bertl
and see what happens with unidirectional data transfer, 32bit on every clock cycle
22:06
Bertl
aSobhy: all the data transfer happens via the j* ports
22:07
apurvanandan[m]
These is the sequence of events : Normal routine ie empty after 14 clocks --> not almost emoty suddenly --> almost full in near time --> full
22:08
apurvanandan[m]
There isn't much left in the code :/
22:08
apurvanandan[m]
It just basic IO handling of FT601
22:09
Bertl
yes, but you are still in bidirectional mode with all the problems it has, no?
22:09
Bertl
(like turn around and idle, etc)
22:09
apurvanandan[m]
No I am not in bidirectional mode at all
22:09
aSobhy
But all j* ports are output except JTDO
22:09
aSobhy
and ER1 must be shifted to the JTAG instruction register
22:09
Bertl
yup, precisely
22:10
Bertl
see the .py which does exactly this
22:10
apurvanandan[m]
I fixed the mode to ACTIVE Transmitting then also this problem was happening
22:10
Bertl
were is the wiki page with all the information you collected? :)
22:10
apurvanandan[m]
And now the code doesn't have any bidirectional or retransmit or any thing like that
22:12
apurvanandan[m]
https://gist.github.com/apurvanandan1997/b61c1f01f17897af8d37ea1b44fb8b8b here is the code , you can see there isn't any bus turn around
22:12
Bertl
what is the config on the other side (PC)?
22:13
apurvanandan[m]
1 IN channerl in FT245 mode
22:19
Bertl
okay, needs more analysis
22:19
Bertl
let's focus on getting the tests working on the Beta for now
22:19
Bertl
this way I can also easily test things
22:22
apurvanandan[m]
Okay, better option
22:22
apurvanandan[m]
Thanks
22:25
Bertl
I'll improve the jtag bypass to make programming the plugin FPGA easier
22:25
Bertl
(shouldn't take too long :)
22:39
apurvanandan[m]
Thanks a lot :D
23:44
Bertl
okay, looks good, do we have a 'blink' bit stream for blinking the LED on the USB plugin module?
23:45
apurvanandan[m]
Hey, aSobhy I wrote a script using which you can easily send files from and to the beta
23:45
apurvanandan[m]
Yes I have that Bertl
23:46
Bertl
@file: what's wrong with scp?
23:48
apurvanandan[m]
Two times scp and writing ports, for download and upload!
23:48
Bertl
you can forward a port with the first ssh
23:48
apurvanandan[m]
Now just one word command for files and folder
23:49
Bertl
something like ssh -L 5555:beta_e:22
23:49
apurvanandan[m]
:O
23:49
Bertl
will allow you to use local port 5555 as if it were port 22 on the beta
23:49
Bertl
@blink please upload and provide the url for testing
23:50
apurvanandan[m]
Ok will see that
23:52
apurvanandan[m]
Both svf and bit files on Beta now
23:52
Bertl
I said url :)
23:52
Bertl
I have a local setup for testing here ...
23:53
apurvanandan[m]
I didn't get you
23:53
apurvanandan[m]
Location of file?
23:53
Bertl
upload it somewhere
23:53
Bertl
nevermind, I copy it from the beta ...
23:54
Bertl
apurva_ws?
23:55
apurvanandan[m]
inside apurva_ws on both zbox and beta_e
23:55
apurvanandan[m]
The folder
23:56
Bertl
yup, works like a charm
23:56
apurvanandan[m]
\o/
23:56
Bertl
let me upload the scripts and provide some explanations
23:56
Bertl
aSobhy: you still around?
23:57
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23:58
apurvanandan[m]
Please test with data_transfer bit file once
23:58
apurvanandan[m]
You will be able to resceive data from ft602
23:58
apurvanandan[m]
ft601