#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

Meeting time!

apoorva_arora: is first in line, please go ahead

Thank you, Last week i submitted the first part of the project. This included PHY layer as well as packet layeer both master slave with a demonstration testbench simulation for SPI Master interface on the slave device. This week i will start my first hardware implementation. Plan will be to test basic data transmission using bidirectional PHY with ZYNQ being master and machxo2 being slave device.

anything to share/show from your first part of the project?

the report describes design, construction as well as validation of the code.

metal_dent[m]: you are next

last week was the evaluation period so i cleaned up my code, added the copyrights, readme and prepared the report for phase I

right now i'm working on the python script as to make the communication work between host and remote, i need to send the commands to the remote which is done using pyserial

that's it from my side!

bluez_[m]: is next in line

so last week I too finalized and submitted the code and report for evaluation

the driver can successfully upload a bitstream into MachXO2

it took me sometime to find a good updated implementation for reference... i finally found it and am almost done with the implementation

sounds good!

thats all from my side!

thanks

would you be so kind and do so on https://wiki.apertus.org/index.php/GSoC_Projects

se6ast1an: sure :)

megora: preetimenghwani[: what about your first evaluation results?

se6ast1an: ah, okay

Hello Everyone!

here is the link to the report -> https://drive.google.com/file/d/1IgMgVa1qXTgKUCgcIUN8ucDhVH27PYqq/view?usp=sharing

Thats it from my side!

megora: please go ahead

About a week ago I've found that the eMMC model project I was using to make a testbench for mu own project also includes the emmc host.

So I decided to use this one as a base to test host - emmc communication at lower speeds, and to try upgrading it in the case of successful tests.

anything else megora?

That's all.

good point rex

megora & preetimenghwani[ please also add your project to https://wiki.apertus.org/index.php/GSoC_Projects

like https://wiki.apertus.org/index.php/USB_3.0_Plugin_Module_Gearwork

we all need to write individual articles like this, right?

you need a wiki account for that, so if you dont have one yet, create one

metal_dent[m]: No no. That article details all four students from 2018. We regrettably didn't do an article like this for 2019. So just a short paragraph and image and we'll build the article.

RexOrCine: okay, thanks! we'll keep this in mind :)

and phase II will be harder

hi everyone

yes, the article will likely happen after GSoC 2020 is over

just a short update from me, as i was busy with other things besides apertus in the last weeks, but my main tasks were gsoc mentoring and PCB panelisation script

latest obstacle is some weird format of the drill positions, but it's more about settings while merging probably

great work! :)

very quick update from me: as I am still a cat nurse currently I didnt get as much done as I hoped I would unfortunately

and I plan to still work on the FW 2.0 usage documentation on the wiki soon

thanks!

not very suprisingly, most of last week was spent on first evaluation and getting everything together regarding GSoC 2020

starting with today we also have a new trainee (from the observatory) working on Axiom related stuff

https://wiki.apertus.org/index.php/Beta_CSO

the IMU CSO features accelerometer, magnetometer, barometer and gyroscope (all MEMs)

other than that, some rework but nothing spectacular

the trainee will mostly work on the software side of the CSO correct?

or gateware if required (IIRC he wants to work on FPGA related stuff)?

the CSO is connected to the routing fabrics

so gateware for the routing FPGAs (MachXO2) is required

Excellent. Have we met him before?

nope, brand new guy

MEETING concluded, many thanks everyone!