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| 04:47 | Bertl_oO | off to bed now ... have a good one everyone!
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| 13:20 | xthenode | BAndiT1983: re: https://wiki.apertus.org/index.php/Beta_Interface_Dummy_Board: very helpful!
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| 13:23 | xthenode | BAndiT1983: it would be interesting on working on an upped version...
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| 13:24 | xthenode | has there ever been discussions on using uclinux on such a device...
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| 13:26 | BAndiT1983 | am less involved in the low-level linux stuff there, at least at the moment, so am the wrong person to ask
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| 13:26 | xthenode | who?
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| 13:27 | BAndiT1983 | Bertl, vup or anuejn probably
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| 13:29 | vup2 | xthenode: what would uclinux be used for there?
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| 13:30 | xthenode | ability to use linux vs embedded os
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| 13:30 | xthenode | ive done both for devices...
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| 13:30 | vup2 | Well what would a os be used for on the interface board?
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| 13:31 | xthenode | it wopuld be nice to have a captured image...
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| 13:32 | xthenode | it would be off to the side of the normal flow...
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| 13:33 | vup2 | The current plan was using a just a fpga without any cpu / softcore and use the fpga as a "stupid" protocol converter between a slower protocol with more lanes to a faster with less lanes
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| 13:34 | vup2 | Can you elaborate what you would use the captured image on the interface board for?
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| 13:35 | xthenode | dlsr controlled by pi
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| 13:37 | BAndiT1983 | xthenode: i suppose that you confuse the interface baord there, it's just for connection of the sensor board to the camera, as lane adapter
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| 13:38 | xthenode | haveing raw an gamma corrected images would be cool
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| 13:38 | BAndiT1983 | if you have another sensor type, then you would just need another sensor board
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| 13:39 | BAndiT1983 | this can happen in post-processing or with simple algorithms on the embedded hardware, vup and anuejn were prototyping something there
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| 13:39 | xthenode | actually the doc says the interface board is designed to be an adapter to raw sensor feed...
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| 13:39 | vup2 | xthenode: Why would you need a os / cpu on the interface board if you want to send the image to a pi anyways, which already has a cpu?
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| 13:40 | xthenode | common tool chain at os level...
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| 13:40 | xthenode | this would be an upped interface...
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| 13:40 | BAndiT1983 | the camera is just a capture device in the base, processing would require additional performance
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| 13:41 | BAndiT1983 | big cameras are also just spitting the data out, which is debayered, color-corrected etc. in post
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| 13:41 | BAndiT1983 | xthenode: where is it saying something about the raw sensor feed? couldn't find the sentence there
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| 13:42 | BAndiT1983 | Â It connects LVDS pairs from the camera's Main Board with the SFE (sensor front end).
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| 13:42 | vup2 | xthenode: i think i don't quite understand what you are trying to do. Do you want to just take the interface board and the SFE board and connect that to a pi? Or are you thinking about something different?
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| 13:42 | BAndiT1983 | purely electronical LVDS connection to grab the data from the connected sensor, no processing on the board
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| 13:43 | xthenode | feed only right?
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| 13:43 | xthenode | no captured image?
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| 13:44 | BAndiT1983 | captured image lands in the buffer of the microzed, if i remember correctly
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| 13:44 | BAndiT1983 | as you have a lot of data and have to control the sensor also, so fpga is used to retrieve the bulk
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| 13:45 | xthenode | yes, and the idea is to put the frame grab down lower...
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| 13:46 | BAndiT1983 | used HDMI feed and snapshot feature through SSH, worked fine
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| 13:46 | xthenode | it would be an addition not replacement to existing design...
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| 13:46 | BAndiT1983 | but am a developer not a user
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| 13:49 | vup2 | xthenode: how would the captured frame be used on the interface board?
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| 13:51 | vup2 | If i understand you correctly you want to just use the SFE board and the interface board and then connect the interface board to a pi, and the pi receives the image?
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| 13:51 | xthenode | vup2: yes use it directly with pi. the captured image would be used by the processing board (pi)
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| 13:52 | BAndiT1983 | the sensor has no buffer or driver, so you need to grab the data somehow, doubt that pi can do it and has enough lanes for that
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| 13:53 | BAndiT1983 | Output Interface: LVDS 64x 600Mbps
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| 13:53 | BAndiT1983 | https://ams.com/cmv12000
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| 13:53 | vup2 | BAndiT1983: you could adapt the sensor signal to mipi which the pi can read
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| 13:53 | xthenode | vup2: this would allow use of the 2 boards in other devices...
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| 13:54 | vup2 | xthenode: then how would a cpu be used on the interface board use a cpu? Why would a fpga not suffice?
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| 13:54 | vup2 | s/use a cpu//
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| 13:54 | xthenode | im willing to work on adding these features...
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| 13:56 | xthenode | fpga is usually used for data flow
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| 13:57 | xthenode | yes, it could be used to do memory cycles to capture image...
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| 13:58 | xthenode | the cpu could be used for gamma correction...
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| 13:58 | xthenode | of the captured image channels
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| 13:58 | vup2 | Why not do it in the fpga? We already do that in the fpga...
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| 13:59 | xthenode | the capture part. yes.
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| 13:59 | vup2 | The gamma correction aswell
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| 14:00 | xthenode | is that as easy in an fpga?
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| 14:01 | vup2 | Well i would say easier as you don't need to get the image from the fpga to the cpu and potentially to the fpga again just to do gamma correction
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| 14:01 | xthenode | fpga would be speediest way...
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| 14:02 | xthenode | so just up fpga and add memory?
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| 14:03 | vup2 | SDRAM? that could be interesting yeah
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| 14:03 | xthenode | yup
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| 14:05 | vup2 | This is the newest dummy interface board: http://files.apertus.org/HARDWARE/AXIOM/BETA/IFACE_BOARD/axiom_beta_interface_dummy_v0.13_r1.1.zip
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| 14:05 | vup2 | You probably want to base the upped version on that.
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| 14:05 | vup2 | Are you using eagle or something else for pcb design
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| 14:06 | xthenode | orcad
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| 14:07 | xthenode | i actually worked in a multi-layer board factory in the past...
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| 14:09 | vup2 | Would you be open to using eagle or kicad? Afaik there is no free version of orcad, so it could be difficult for others to use the files then
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| 14:09 | xthenode | totally...
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| 14:10 | xthenode | im running on mac, linux and windows...
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| 14:10 | vup2 | Cool. I think Bertl will have some input on the design of the upped version of the interface board
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| 14:11 | xthenode | cool
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| 14:11 | BAndiT1983 | http://vserver.13thfloor.at/Stuff/AXIOM/BETA/PANEL/
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| 14:11 | vup2 | xthenode: do you think it could be done on 4 layers (fpga + ram) or at minimum 6?
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| 14:11 | BAndiT1983 | in case you're interested in the latest versions of the boards and schematics
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| 14:13 | xthenode | re: xthenode: do you think it could be done on 4 layers (fpga + ram) or at minimum 6? not sure at this point
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| 14:14 | xthenode | what do you use for the verilog part?
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| 14:16 | xthenode | BAndiT1983: thanks
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| 14:16 | BAndiT1983 | VHDL is used primarily
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| 14:17 | xthenode | VHDL: what translator / compiler?
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| 14:18 | BAndiT1983 | xilinx vivado, but vup2 can correct me there
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| 14:18 | xthenode | or, is it delivered to factory?
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| 14:18 | BAndiT1983 | which factory?
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| 14:18 | xthenode | makers of the boards
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| 14:19 | BAndiT1983 | please elaborate
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| 14:19 | xthenode | chip makers
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| 14:20 | BAndiT1983 | ?
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| 14:20 | BAndiT1983 | just some terms are not really explaining your question
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| 14:20 | xthenode | looks like you are using xilinx vivado for xlation...
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| 14:21 | xthenode | ie VHDL to FPGA programming
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| 14:22 | BAndiT1983 | https://github.com/apertus-open-source-cinema/axiom-firmware/tree/master/peripherals
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| 14:22 | BAndiT1983 | as the toolchains are restricted, the streams are provided as binaries, if i remember correctly
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| 14:22 | BAndiT1983 | so no CI or similar
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| 14:23 | vup2 | xthenode: yes vivado for the xilinx fpgas, diamond for the lattice fpgas
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| 14:23 | xthenode | got it
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| 14:24 | vup2 | BAndiT1983: actually we have CI with vivado, just not hooked up to axiom-firmware yet
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| 14:25 | BAndiT1983 | vup2: ok, my knowledge seems to be outdated in this area
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| 14:26 | xthenode | vup2: so let me know if, how and when i should add to the project...
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| 14:27 | vup2 | xthenode: i think talking to Bertl to get his ideas on the interface board and then designing the new pcb would be great
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| 14:28 | xthenode | cool. how. chat?
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| 14:28 | xthenode | meet?
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| 14:28 | xthenode | teams?
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| 14:29 | vup2 | Yes IRC is probably the best option, just need to wait for him to wake up
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| 14:29 | xthenode | cool
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| 14:29 | xthenode | ill check logs...
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| 14:29 | xthenode | off for now...
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| 14:29 | vup2 | Sure. Maybe you want to get a irc bouncer setup aswell
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| 14:30 | xthenode | how?
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| 14:30 | xthenode | will do?
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| 14:31 | xthenode | left the channel |
| 14:38 | vup2 | Hmm I thought we had a wiki page for that
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| 14:38 | vup2 | Maybe lookup znc or quassel
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| 14:45 | Bertl_zZ | changed nick to: Bertl
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| 14:45 | Bertl | morning folks!
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| 14:46 | BAndiT1983 | hi
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| 18:11 | xthenode | vup2: znc...
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| 18:13 | xthenode | Bertl: you see discussion on upped iface board?
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| 18:16 | Bertl | not yet
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| 18:16 | xthenode | k
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