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#apertus IRC Channel Logs

2021/01/06

Timezone: UTC


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Bertl_oO
off to bed now ... have a good one everyone!
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Bertl_oO
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BAndiT1983|away
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se6ast1an
good day
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12:19
xthenode
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12:20
xthenode
BAndiT1983: re: https://wiki.apertus.org/index.php/Beta_Interface_Dummy_Board: very helpful!
12:23
xthenode
BAndiT1983: it would be interesting on working on an upped version...
12:24
xthenode
has there ever been discussions on using uclinux on such a device...
12:26
BAndiT1983
am less involved in the low-level linux stuff there, at least at the moment, so am the wrong person to ask
12:26
xthenode
who?
12:27
BAndiT1983
Bertl, vup or anuejn probably
12:29
vup2
xthenode: what would uclinux be used for there?
12:30
xthenode
ability to use linux vs embedded os
12:30
xthenode
ive done both for devices...
12:30
vup2
Well what would a os be used for on the interface board?
12:31
xthenode
it wopuld be nice to have a captured image...
12:32
xthenode
it would be off to the side of the normal flow...
12:33
vup2
The current plan was using a just a fpga without any cpu / softcore and use the fpga as a "stupid" protocol converter between a slower protocol with more lanes to a faster with less lanes
12:34
vup2
Can you elaborate what you would use the captured image on the interface board for?
12:35
xthenode
dlsr controlled by pi
12:37
BAndiT1983
xthenode: i suppose that you confuse the interface baord there, it's just for connection of the sensor board to the camera, as lane adapter
12:38
xthenode
haveing raw an gamma corrected images would be cool
12:38
BAndiT1983
if you have another sensor type, then you would just need another sensor board
12:39
BAndiT1983
this can happen in post-processing or with simple algorithms on the embedded hardware, vup and anuejn were prototyping something there
12:39
xthenode
actually the doc says the interface board is designed to be an adapter to raw sensor feed...
12:39
vup2
xthenode: Why would you need a os / cpu on the interface board if you want to send the image to a pi anyways, which already has a cpu?
12:40
xthenode
common tool chain at os level...
12:40
xthenode
this would be an upped interface...
12:40
BAndiT1983
the camera is just a capture device in the base, processing would require additional performance
12:41
BAndiT1983
big cameras are also just spitting the data out, which is debayered, color-corrected etc. in post
12:41
BAndiT1983
xthenode: where is it saying something about the raw sensor feed? couldn't find the sentence there
12:42
BAndiT1983
 It connects LVDS pairs from the camera's Main Board with the SFE (sensor front end).
12:42
vup2
xthenode: i think i don't quite understand what you are trying to do. Do you want to just take the interface board and the SFE board and connect that to a pi? Or are you thinking about something different?
12:42
BAndiT1983
purely electronical LVDS connection to grab the data from the connected sensor, no processing on the board
12:43
xthenode
feed only right?
12:43
xthenode
no captured image?
12:44
BAndiT1983
captured image lands in the buffer of the microzed, if i remember correctly
12:44
BAndiT1983
as you have a lot of data and have to control the sensor also, so fpga is used to retrieve the bulk
12:45
xthenode
yes, and the idea is to put the frame grab down lower...
12:46
BAndiT1983
used HDMI feed and snapshot feature through SSH, worked fine
12:46
xthenode
it would be an addition not replacement to existing design...
12:46
BAndiT1983
but am a developer not a user
12:49
vup2
xthenode: how would the captured frame be used on the interface board?
12:51
vup2
If i understand you correctly you want to just use the SFE board and the interface board and then connect the interface board to a pi, and the pi receives the image?
12:51
xthenode
vup2: yes use it directly with pi. the captured image would be used by the processing board (pi)
12:52
BAndiT1983
the sensor has no buffer or driver, so you need to grab the data somehow, doubt that pi can do it and has enough lanes for that
12:53
BAndiT1983
Output Interface: LVDS 64x 600Mbps
12:53
BAndiT1983
https://ams.com/cmv12000
12:53
vup2
BAndiT1983: you could adapt the sensor signal to mipi which the pi can read
12:53
xthenode
vup2: this would allow use of the 2 boards in other devices...
12:54
vup2
xthenode: then how would a cpu be used on the interface board use a cpu? Why would a fpga not suffice?
12:54
vup2
s/use a cpu//
12:54
xthenode
im willing to work on adding these features...
12:56
xthenode
fpga is usually used for data flow
12:57
xthenode
yes, it could be used to do memory cycles to capture image...
12:58
xthenode
the cpu could be used for gamma correction...
12:58
xthenode
of the captured image channels
12:58
vup2
Why not do it in the fpga? We already do that in the fpga...
12:59
xthenode
the capture part. yes.
12:59
vup2
The gamma correction aswell
13:00
xthenode
is that as easy in an fpga?
13:01
vup2
Well i would say easier as you don't need to get the image from the fpga to the cpu and potentially to the fpga again just to do gamma correction
13:01
xthenode
fpga would be speediest way...
13:02
xthenode
so just up fpga and add memory?
13:03
vup2
SDRAM? that could be interesting yeah
13:03
xthenode
yup
13:05
vup2
This is the newest dummy interface board: http://files.apertus.org/HARDWARE/AXIOM/BETA/IFACE_BOARD/axiom_beta_interface_dummy_v0.13_r1.1.zip
13:05
vup2
You probably want to base the upped version on that.
13:05
vup2
Are you using eagle or something else for pcb design
13:06
xthenode
orcad
13:07
xthenode
i actually worked in a multi-layer board factory in the past...
13:09
vup2
Would you be open to using eagle or kicad? Afaik there is no free version of orcad, so it could be difficult for others to use the files then
13:09
xthenode
totally...
13:10
xthenode
im running on mac, linux and windows...
13:10
vup2
Cool. I think Bertl will have some input on the design of the upped version of the interface board
13:11
xthenode
cool
13:11
BAndiT1983
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/PANEL/
13:11
vup2
xthenode: do you think it could be done on 4 layers (fpga + ram) or at minimum 6?
13:11
BAndiT1983
in case you're interested in the latest versions of the boards and schematics
13:13
xthenode
re: xthenode: do you think it could be done on 4 layers (fpga + ram) or at minimum 6? not sure at this point
13:14
xthenode
what do you use for the verilog part?
13:16
xthenode
BAndiT1983: thanks
13:16
BAndiT1983
VHDL is used primarily
13:17
xthenode
VHDL: what translator / compiler?
13:18
BAndiT1983
xilinx vivado, but vup2 can correct me there
13:18
xthenode
or, is it delivered to factory?
13:18
BAndiT1983
which factory?
13:18
xthenode
makers of the boards
13:19
BAndiT1983
please elaborate
13:19
xthenode
chip makers
13:20
BAndiT1983
?
13:20
BAndiT1983
just some terms are not really explaining your question
13:20
xthenode
looks like you are using xilinx vivado for xlation...
13:21
xthenode
ie VHDL to FPGA programming
13:22
BAndiT1983
https://github.com/apertus-open-source-cinema/axiom-firmware/tree/master/peripherals
13:22
eppisai
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13:22
BAndiT1983
as the toolchains are restricted, the streams are provided as binaries, if i remember correctly
13:22
BAndiT1983
so no CI or similar
13:22
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13:23
vup2
xthenode: yes vivado for the xilinx fpgas, diamond for the lattice fpgas
13:23
xthenode
got it
13:24
vup2
BAndiT1983: actually we have CI with vivado, just not hooked up to axiom-firmware yet
13:25
BAndiT1983
vup2: ok, my knowledge seems to be outdated in this area
13:26
xthenode
vup2: so let me know if, how and when i should add to the project...
13:27
vup2
xthenode: i think talking to Bertl to get his ideas on the interface board and then designing the new pcb would be great
13:28
xthenode
cool. how. chat?
13:28
xthenode
meet?
13:28
xthenode
teams?
13:29
vup2
Yes IRC is probably the best option, just need to wait for him to wake up
13:29
xthenode
cool
13:29
xthenode
ill check logs...
13:29
xthenode
off for now...
13:29
vup2
Sure. Maybe you want to get a irc bouncer setup aswell
13:30
xthenode
how?
13:30
xthenode
will do?
13:31
xthenode
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13:38
vup2
Hmm I thought we had a wiki page for that
13:38
vup2
Maybe lookup znc or quassel
13:45
Bertl_zZ
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13:45
Bertl
morning folks!
13:46
BAndiT1983
hi
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BAndiT1983
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17:11
xthenode
vup2: znc...
17:13
xthenode
Bertl: you see discussion on upped iface board?
17:16
Bertl
not yet
17:16
xthenode
k
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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xthenode
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BAndiT1983
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