#apertus IRC Channel Logs

BAndiT1983: it would be interesting on working on an upped version...

am less involved in the low-level linux stuff there, at least at the moment, so am the wrong person to ask

Bertl, vup or anuejn probably

ability to use linux vs embedded os

Well what would a os be used for on the interface board?

it would be off to the side of the normal flow...

Can you elaborate what you would use the captured image on the interface board for?

xthenode: i suppose that you confuse the interface baord there, it's just for connection of the sensor board to the camera, as lane adapter

if you have another sensor type, then you would just need another sensor board

actually the doc says the interface board is designed to be an adapter to raw sensor feed...

common tool chain at os level...

the camera is just a capture device in the base, processing would require additional performance

xthenode: where is it saying something about the raw sensor feed? couldn't find the sentence there

xthenode: i think i don't quite understand what you are trying to do. Do you want to just take the interface board and the SFE board and connect that to a pi? Or are you thinking about something different?

feed only right?

captured image lands in the buffer of the microzed, if i remember correctly

yes, and the idea is to put the frame grab down lower...

it would be an addition not replacement to existing design...

xthenode: how would the captured frame be used on the interface board?

vup2: yes use it directly with pi. the captured image would be used by the processing board (pi)

Output Interface: LVDS 64x 600Mbps

BAndiT1983: you could adapt the sensor signal to mipi which the pi can read

xthenode: then how would a cpu be used on the interface board use a cpu? Why would a fpga not suffice?

im willing to work on adding these features...

yes, it could be used to do memory cycles to capture image...

of the captured image channels

the capture part. yes.

is that as easy in an fpga?

fpga would be speediest way...

SDRAM? that could be interesting yeah

This is the newest dummy interface board: http://files.apertus.org/HARDWARE/AXIOM/BETA/IFACE_BOARD/axiom_beta_interface_dummy_v0.13_r1.1.zip

Are you using eagle or something else for pcb design

i actually worked in a multi-layer board factory in the past...

totally...

Cool. I think Bertl will have some input on the design of the upped version of the interface board

http://vserver.13thfloor.at/Stuff/AXIOM/BETA/PANEL/

in case you're interested in the latest versions of the boards and schematics

what do you use for the verilog part?

VHDL is used primarily

xilinx vivado, but vup2 can correct me there

which factory?

please elaborate

?

looks like you are using xilinx vivado for xlation...

https://github.com/apertus-open-source-cinema/axiom-firmware/tree/master/peripherals

as the toolchains are restricted, the streams are provided as binaries, if i remember correctly

got it

vup2: ok, my knowledge seems to be outdated in this area

xthenode: i think talking to Bertl to get his ideas on the interface board and then designing the new pcb would be great

meet?

Yes IRC is probably the best option, just need to wait for him to wake up

ill check logs...

Sure. Maybe you want to get a irc bouncer setup aswell

will do?

Hmm I thought we had a wiki page for that

hi

vup2: znc...

not yet