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| 04:00 | Bertl_oO | off to bed now ... have a good one everyone!
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| 11:31 | Bertl | morning folks!
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| 19:10 | tpw_rules | vup and anuejn: i am looking into how to implement the cmv12000 interface in nmigen and it looks like this PR will be needed for a clean implementation: https://github.com/nmigen/nmigen/pull/514
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| 19:11 | tpw_rules | it also looks like the LVDS bus is split across the two connectors so i will have to specify the FPGA pad names directly
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| 19:11 | tpw_rules | another option is to programmatically generate lvds_in_0 through 31 or whatever and concatenate all of them together. fortunately that is easy in nmigen but also ugly. thoughts?
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| 19:12 | tpw_rules | where "implement the cmv12000 interface" = describe it as a Resource on the BetaPlatform
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| 19:13 | tpw_rules | Bertl: how are the sensors coming along? if you think it will take more than another week, i think it would be great if you could attach something SPI to the sensor SPI pins so i can validate the interface.
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| 19:14 | Bertl | I'll do that anyway, but it isn't looking too bad for the sensor beta either
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| 19:15 | tpw_rules | ok. just something i can read and write to. a wire between the in and out pins might be good enough, but that wouldn't test CS :)
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| 19:19 | tpw_rules | anuejn: is there information or a demo on how to use your ILA? it would be good to validate the spi pin outputs too
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| 19:19 | tpw_rules | (does it work on the real hardware?)
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| 20:29 | se6astian | Oshpark 6 layers is now a regular service!
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| 20:30 | se6astian | https://blog.oshpark.com/2021/06/04/new-6-layer-pcb-service-now-from-osh-park/
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| 20:34 | tpw_rules | https://github.com/apertus-open-source-cinema/naps/blob/70c543466838652119d9d7f22fb902a89d7e4eef/naps/cores/peripherals/bitbang_i2c.py#L22 what is the significance of "6" here? i assume bit 1 set means it's open drain because it's i2c, but what is bit 2?
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| 21:27 | Bertl | se6astian: \o/
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| 22:41 | anuejn | tpw_rules: yeah that pr would be quite handy indeed
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| 22:42 | anuejn | I think that describing them as lvds_in_0 through 32 would be the cleanest way for now
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| 22:44 | anuejn | to use that ila you can have a look at my wip mipi dsi code https://github.com/apertus-open-source-cinema/naps/blob/dac7ad68388352de7d162e375a36b1e72e169a21/naps/cores/mipi/d_phy_lane.py#L94-L99
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| 22:45 | anuejn | you then need to instanciate the ila in your top level with `add_ila(platform, domain="sampling_domain")`
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| 22:45 | anuejn | by default the trigger event will be centered in the sampling window of the ila
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| 22:46 | anuejn | to get the csv file of your ila, simply arm the trigger of the ila with `design.ila.arm()` in the pydriver repl
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| 22:47 | anuejn | and get the captured waveforms after a trigger with `design.ila.write_vcd()`
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| 22:48 | anuejn | currently the ila silently breaks if the number of bits you probe exceeds 32 (stupid limitation of SocMemory)
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| 22:48 | anuejn | (also you can probe fsm state with decoding with https://github.com/apertus-open-source-cinema/naps/blob/dac7ad68388352de7d162e375a36b1e72e169a21/naps/cores/mipi/d_phy_lane.py#L110)
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| 22:50 | tpw_rules | how do i set the depth?
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| 22:56 | anuejn | add_ila forwards its arguments to Ila
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| 22:56 | anuejn | so trace_length is it (and you can set the trigger point in the trace with after_trigger)
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| 23:04 | anuejn | does it work?
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