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17:15 | Bertl | evening folks!
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17:16 | se6astian | hello!
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17:16 | se6astian | https://wiki.apertus.org/index.php?title=HDMI-Test
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17:16 | se6astian | I have a beautiful test pattern on my 46" LCD :D
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17:17 | Bertl | hehe :)
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17:17 | Bertl | instead of the pink push button a 'reset' command should work as well
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17:18 | Bertl | did you try to play with the switches?
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17:18 | Bertl | and did you like the oled logo?
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17:19 | se6astian | yes I played with the switches
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17:19 | se6astian | love the OLED!
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17:20 | Bertl | so the lower 4 switches select the pattern, while the upper four modify the size
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17:21 | se6astian | but ther rightmost buttons also create an all red, blue, green image
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17:21 | se6astian | and you can also create strips and line patterns
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17:21 | se6astian | very nice
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17:21 | Bertl | yes, that is one of the patterns
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17:22 | Bertl | i.e. black, red, green, blue, lines h/v/both, bars h/v and checkers
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17:22 | se6astian | ah yes
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17:22 | Bertl | and finally the composite test pattern
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17:22 | se6astian | works great!
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17:23 | Bertl | so the idea is to check this on different displays and if necessary adjust the timing parameters
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17:23 | Bertl | there is, for example, a configuration for 1280x768 as well :)
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17:24 | Bertl | which can be activated by:
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17:24 | Bertl | /usr/script/gen1280_init.sh
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17:25 | Bertl | if you unplug and replug a display, you need to execute
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17:25 | Bertl | /usr/script/adv7511_init.sh
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17:25 | Bertl | and finally, you can adjust the pixel clock with:
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17:26 | se6astian | my display doesnt like gen1280_init.sh
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17:26 | Bertl | echo 135000000 >/sys/class/fclk/FPGA2/set_rate
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17:26 | se6astian | it says "non optimal mode, change resolution to 1920x1080..."
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17:26 | Bertl | well, the 1280x768 are transmitted with more than 100Hz
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17:26 | Bertl | so it might need a change to the clock rate, like:
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17:26 | Bertl | echo 75000000 >/sys/class/fclk/FPGA2/set_rate
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17:27 | Bertl | note that the fclks do not support arbitrary clock rates, i.e. there is no difference between 135MHz and 140MHz for example
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17:27 | Bertl | the selected rate can be read back from /sys/class/fclk/FPGA2/set_rate
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17:28 | se6astian | haha, it works in 1280 mode now!
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17:29 | se6astian | very nice!
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17:31 | se6astian | Did you see that Elphel also started prototyping zynq with a microzed board
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17:32 | Bertl | yep, I read the blog article you forwarded
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17:40 | Bertl | ah, I forgot to explain the registers:
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17:42 | Bertl | http://pastebin.com/e83HYNRL
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17:47 | se6astian | added
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17:57 | Bertl | thanks!
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17:57 | Bertl | off for a nap ... bbl
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