Current Server Time: 23:10 (Central Europe)

#apertus IRC Channel Logs

2013/10/04

Timezone: UTC


07:22
se6astian
joined the channel
15:43
[1]se6astian
joined the channel
15:46
se6astian
left the channel
15:46
[1]se6astian
changed nick to: se6astian
15:54
se6astian
left the channel
16:43
se6astian
joined the channel
17:15
Bertl
evening folks!
17:16
se6astian
hello!
17:16
se6astian
https://wiki.apertus.org/index.php?title=HDMI-Test
17:16
se6astian
I have a beautiful test pattern on my 46" LCD :D
17:17
Bertl
hehe :)
17:17
Bertl
instead of the pink push button a 'reset' command should work as well
17:18
Bertl
did you try to play with the switches?
17:18
Bertl
and did you like the oled logo?
17:19
se6astian
yes I played with the switches
17:19
se6astian
love the OLED!
17:20
Bertl
so the lower 4 switches select the pattern, while the upper four modify the size
17:21
se6astian
but ther rightmost buttons also create an all red, blue, green image
17:21
se6astian
and you can also create strips and line patterns
17:21
se6astian
very nice
17:21
Bertl
yes, that is one of the patterns
17:22
Bertl
i.e. black, red, green, blue, lines h/v/both, bars h/v and checkers
17:22
se6astian
ah yes
17:22
Bertl
and finally the composite test pattern
17:22
se6astian
works great!
17:23
Bertl
so the idea is to check this on different displays and if necessary adjust the timing parameters
17:23
Bertl
there is, for example, a configuration for 1280x768 as well :)
17:24
Bertl
which can be activated by:
17:24
Bertl
/usr/script/gen1280_init.sh
17:25
Bertl
if you unplug and replug a display, you need to execute
17:25
Bertl
/usr/script/adv7511_init.sh
17:25
Bertl
and finally, you can adjust the pixel clock with:
17:26
se6astian
my display doesnt like gen1280_init.sh
17:26
Bertl
echo 135000000 >/sys/class/fclk/FPGA2/set_rate
17:26
se6astian
it says "non optimal mode, change resolution to 1920x1080..."
17:26
Bertl
well, the 1280x768 are transmitted with more than 100Hz
17:26
Bertl
so it might need a change to the clock rate, like:
17:26
Bertl
echo 75000000 >/sys/class/fclk/FPGA2/set_rate
17:27
Bertl
note that the fclks do not support arbitrary clock rates, i.e. there is no difference between 135MHz and 140MHz for example
17:27
Bertl
the selected rate can be read back from /sys/class/fclk/FPGA2/set_rate
17:28
se6astian
haha, it works in 1280 mode now!
17:29
se6astian
very nice!
17:31
se6astian
Did you see that Elphel also started prototyping zynq with a microzed board
17:32
Bertl
yep, I read the blog article you forwarded
17:40
Bertl
ah, I forgot to explain the registers:
17:42
Bertl
http://pastebin.com/e83HYNRL
17:47
se6astian
added
17:57
Bertl
thanks!
17:57
Bertl
off for a nap ... bbl
21:08
se6astian
left the channel