#apertus IRC Channel Logs

I searched alot but can't find how to add them

I download the files

the board definition files?

and did you unpack them in the proper location?

as described in the readme?

the pdf is title 'Install Avnet Board Definition Files in ...'

http://zedboard.org/sites/default/files/documentations/Avnet%20Zed%20Board%20Defnition%20Files.zip

every time you prove that I have to ask first xD

(not that it is hard to find with google :)

I was on that link :( and every page I opened was referring to the same link

via I2C

i2c0_bit_clr 0x22 0x15 7 sleep 0.1 i2c0_bit_set 0x22 0x15 7

that's the GPIO extender. not the pic

ah okay sorry

didn't dig through it I have an error at the bit stream generation "[DRC NSTD-1]"

yes

set_property IOSTANDARD LVCMOS25 [get_ports {spi_*}]

for example

btw, when did you last work with the remote beta?

and when was the last time you flashed one of the MachXO2s?

yeah, looks like ...

Bertl, we can't just replicate the current system 5 times for 5 lanes as we have only 2 DQSDLL and 4 ECLKSYNC available on machXO2

Good morning Bertl

This is IPexpress implementation is this : https://ibb.co/D7m6N08

that is kind of what I expected ...

Also I have a idea

Described on page 33 of TN1203

high-speed edge clock cycle to maintain the clock domain crossing margin between ECLK and SCLK, and to avoid

So it does reset syncronisation

and all the reset pins are directly conencted to your reset input

I think there is some mistake

that would make a lot more sense to me :)

on your side?

okay :)

Bertl, I have an idea can we use 40 bits recieved from 5 channels as 4 encoded words which would result in 4 8 bits decoded words that is 32 bits :)

but you are spreading the 8b10b codes over different channels then

i.e. you might be better off with dropping the encoding and just signalling control codes

Yes

and you probably want to train the LVDS channels individually

as they will have different wire lengths

ok I will select delayd there

so it can't be responsible for the reset sequence, no?

It was written it is responsible for that

@rx_sync: well, it is neither connected to the reset input nor to the other resets, so we can rule out that it does anything about reset synchronization

which brings me to the question what the DQSDLLC does

Yes i remember we need to find center of eye, but how can we do that with current setup?

Or maybe rx_sync is looking after those, but I have set uddcntln to constant zero

so you are enabling the DQSDLLC with UDDCNTL# low

Yupp Bertl thats the thing

Okay I will try connecting rx_reset with reset of IDDR

https://ibb.co/51nSvD4

each of them will generate data at the same clock rate so they will be in a constant phase relation

with a little luck, you calculate those and properly adjust for them with fixed delay elements (at least up to a certain frequency and under specific conditions)

now you need to put all those delays into constraints (input on the MachXO2 side, output on the Zynq side) to get in the correct ballpark for properly receiving the data

checking different data channels independantly might give some clues here as they will have slightly different delays :)

the DELAYE is static, you can't change it once it is set

Once for all

what about changes in temperature or power, etc

you want to load a new bitstream?

we do not calculate it, we adjust it

not required, but could be an option for testing

one is to use a training pattern in regular intervals and during transmission of this pattern, the delays are adjusted to reproduce the pattern as good as possible

e.g. with the x4 DDR, you get 8 samples of the signal at specific positions

then every second bit will be a transition i.e. an unstable state

this additional information can be used to assert the quality of the delay adjustment

01010101 (data bits)

what does that say about your sampling point? (i.e. the delay)

____/~~~~\____/~~~~\____/~~~~

0_0/~1~1~_0_0_/~1~1~_0_0_/~1~1~

yeah, so is your sampling optimal? i.e. centered on the data?

because your sampling happens at regularily spaced intervals

ideally you would be sampling as far away from any transition point

\___0___/~~~1~~~\___0___/~~~1~~~\

Yeah this is clear

this also means that if your pattern is like the above

you are not perfectly aligned and you want to shift your sample point

similarily when you get a 0110011001100 pattern

so with a little statistic, you can create a locked loop which will dynamically adjust the perfect sampling point

Ok so I what I conclude : I will keep transmitting link pattern for sometime after the word alignment is right. In that time I will calculate ber multiple times with different delay values and set the finall delay value which offer statistically minimum error

i.e. first send an alternating bit pattern

then switch to a word pattern and do the word alignment

so there is no need for a feedback or similar

you can also use a pattern which combines bit and word pattern

I can try with each of these values and find BER?

imagine the info screen on the Beta: "link adjusting ... please be patient, BER at 10^-13"

XD lol

and this will give you a pattern like this:

where _ is just wrong and ~ means looks right

________~_~_~~~~~~~_~___

ah this makes sense

certainly one approach

i.e. moving two sample points till both are on the stable border

or just sample the correct receptions per delay value

you can also out source the calculations to the Zynq PS

the first step should be 'manual' adjustment and BER testing

Can I make direct connections of GPIOs ti my Virtex board?

This is really cool

high speed clock

There was one more method other than oversampling iirc

yes, ECC and dynamic adjustments based on the corrected error rate

by using error correction codes, you can prevent this from affecting your data

and you can do fine adjustments to the delay and observe the effect on the error rate

ahh, nice method

so if you go for the external delay adjustments

then simply do a fixed count of data transfers, e.g. 10^9 at a rate where you definitely get BER

and put that into a graph 'delay vs BER'

if you are hitting 0 BER way too often, increase the data rate :)

because I'm getting error DRC UCIO-1 for not assigning a location to the clk port

"get_ports {clk}"

that is a port 'named' 'clk' on which pin is it?

where does it come from?

you mean, clocks come out of nowhere and just happen to be there?

so, if you state there is a clock called sysClk with 100MHz, you need to specify where it comes from

But create clock will create a clock from the internal oscillator right ?

create_clock will create a new definition for a clock network

it is purely a constraint

how can I map that to its oscillator ?

ZYNQ

the zynq has only a very limited internal oscillator and usually depends on external ones

Is the clock coming from the power board ?!

http://zedboard.org/sites/default/files/documentations/5276-MicroZed-HW-UG-v1-7-V1.pdf

there is no FPGA specific clock on the MicroZed and we do not add one in the Beta

(see http://vserver.13thfloor.at/Stuff/AXIOM/BETA/blink_fclk/ as example)

the code should be self documenting :)

ahh, I get it

yes

I'll do that

yes I get it :)

it can be used for clocking simple designs, but it is not suitable for any high speed stuff

Yes Bertl thats right, some lanes are outperforming others in terms of BER

Bit alignment from page 6 of XAPP600 : exactly what is needed

1 or 2 32 bit values

what is your data rate on both sides of the FIFO?

On read side we have 32 bit width at 100 MHz

okay, so you are not overloading the FIFO

yupp

Also I should reset read pointer once in starting thats all ?

Sorry not 1-2 but many values are lost in chunks eg after 150MBs received 100 words are lost and again 120 MBs received correctly.

Less frequently but lose occurs and in chunks

I didn't get you

do you have anything else on the USB except for the FTDI?

so this might cause the data drops

Let me try that

I am acheiving 300MBps bandwitdh from FT601

the main question is: can a drop be detected?