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#apertus IRC Channel Logs

2019/08/04

Timezone: UTC


01:08
Fares
left the channel
01:43
WalterZimmermann
left the channel
01:50
abeljj[m]
left the channel
03:10
aSobhy
Bertl I get lost I think its because I didn't add the part 7020
03:11
aSobhy
I searched alot but can't find how to add them
03:11
Bertl_oO
hmm?
03:11
aSobhy
I download the files
03:11
aSobhy
downloaded*
03:12
Bertl_oO
the board definition files?
03:12
aSobhy
yes
03:12
Bertl_oO
and did you unpack them in the proper location?
03:13
aSobhy
what location ?!
03:13
Bertl_oO
as described in the readme?
03:14
Bertl_oO
if you unpack the archive, there is a PDF and another archive
03:14
Bertl_oO
the pdf is title 'Install Avnet Board Definition Files in ...'
03:15
aSobhy
no their are two files only .xml
03:16
Bertl_oO
http://zedboard.org/sites/default/files/documentations/Avnet%20Zed%20Board%20Defnition%20Files.zip
03:19
aSobhy
thanks :)
03:20
aSobhy
every time you prove that I have to ask first xD
03:21
Bertl_oO
well, I gave you the link where this archive is yesterday
03:22
Bertl_oO
(not that it is hard to find with google :)
03:23
Bertl_oO
anyway, you're welcome
03:32
aSobhy
I was on that link :( and every page I opened was referring to the same link
03:45
aSobhy
how can I toggle a pin by the PIC16?
03:45
Bertl_oO
via I2C
03:47
Bertl_oO
there is a tool called pic_gpio.py
03:47
aSobhy
i2c0_bit_clr 0x22 0x15 7 sleep 0.1 i2c0_bit_set 0x22 0x15 7
03:48
aSobhy
like that
03:48
Bertl_oO
that's the GPIO extender. not the pic
03:49
Bertl_oO
i.e. wrong I2C bus
03:49
aSobhy
ah okay sorry
03:52
illwieckz
left the channel
03:55
illwieckz
joined the channel
04:57
Bertl_oO
did the script work for your purpose?
05:12
aSobhy
didn't dig through it I have an error at the bit stream generation "[DRC NSTD-1]"
05:14
Bertl_oO
unspecified I/O standard?
05:14
aSobhy
yes
05:15
Bertl_oO
well, specify the IO standard for the listed pins
05:17
aSobhy
set_property IOSTANDARD LVCMOS25 [get_ports {spi_*}]
05:17
aSobhy
like that
05:17
Bertl_oO
for example
05:18
aSobhy
OK
05:24
Bertl_oO
btw, when did you last work with the remote beta?
05:24
aSobhy
16 mins
05:25
Bertl_oO
and when was the last time you flashed one of the MachXO2s?
05:25
aSobhy
along time !
05:26
Bertl_oO
yeah, looks like ...
05:31
Bertl_oO
anyway, off to bed now ... have a good one everyone!
05:31
Bertl_oO
changed nick to: Bertl_zZ
05:34
aSobhy
nn :)
08:55
BAndiT1983|away
changed nick to: BAndiT1983
09:40
Y|_G
joined the channel
09:42
Y_|G
left the channel
10:12
Nira|away
changed nick to: Nira
12:29
apurvanandan[m]
Bertl, we can't just replicate the current system 5 times for 5 lanes as we have only 2 DQSDLL and 4 ECLKSYNC available on machXO2
12:29
apurvanandan[m]
We need to use IPexpress implementation only
12:45
BAndiT1983
changed nick to: BAndiT1983|away
12:45
Nira
changed nick to: Nira|away
13:30
Bertl_zZ
changed nick to: Bertl
13:30
Bertl
morning folks!
13:31
apurvanandan[m]
Good morning Bertl
13:31
Bertl
apurvanandan[m]: and what 'magic' do you think does IPexpress do to make it happen?
13:31
apurvanandan[m]
This is IPexpress implementation is this : https://ibb.co/D7m6N08
13:32
apurvanandan[m]
There isn't any magic about IPexpress, I am just saying we need to use everything once except the IDDR4XB
13:33
Bertl
that is kind of what I expected ...
13:34
apurvanandan[m]
Yupp, this is correct. I will go with this only.
13:34
apurvanandan[m]
Also I have a idea
13:34
Bertl
note: I still do not know what the rx_sync really does?
13:35
apurvanandan[m]
Described on page 33 of TN1203
13:37
apurvanandan[m]
It is therefore necessary to make sure all the components, such as CLKDIV and IDDR/ODDR, start with the same
13:37
apurvanandan[m]
high-speed edge clock cycle to maintain the clock domain crossing margin between ECLK and SCLK, and to avoid
13:37
apurvanandan[m]
bus bit-order scrambling due to the various delay of the reset pulse.
13:37
apurvanandan[m]
So it does reset syncronisation
13:38
Bertl
but in your schematic, the reset pin of the rx_sync is not even connected, no?
13:40
Bertl
and all the reset pins are directly conencted to your reset input
13:40
apurvanandan[m]
Basically, the rx_stop stops the eclk, and external reset is provided
13:40
apurvanandan[m]
I think there is some mistake
13:42
apurvanandan[m]
rx_reset should be joined to reset of all modules after dlldelc
13:42
Bertl
that would make a lot more sense to me :)
13:42
apurvanandan[m]
Probably this was result of code cleanup lol
13:43
Bertl
on your side?
13:43
apurvanandan[m]
Yes
13:43
Bertl
okay :)
13:43
Bertl
I'd double check with a newly IPexpress generated soft IP (i.e. create a schematic for that and compare it)
13:44
apurvanandan[m]
Bertl, I have an idea can we use 40 bits recieved from 5 channels as 4 encoded words which would result in 4 8 bits decoded words that is 32 bits :)
13:45
Bertl
sure
13:45
Bertl
but you are spreading the 8b10b codes over different channels then
13:46
Bertl
(which kind of defeats the purpose)
13:46
Bertl
i.e. you might be better off with dropping the encoding and just signalling control codes
13:46
apurvanandan[m]
So 32bits -> encode -> 40 bits -> transmit on 5 channels -> receive -> 40 bits -> decode -> 32 bits -> FTDI
13:46
apurvanandan[m]
Yes
13:48
apurvanandan[m]
Yup
13:48
Bertl
and you probably want to train the LVDS channels individually
13:49
apurvanandan[m]
Is there anyway we can make use of these ratios
13:49
Bertl
as they will have different wire lengths
13:49
Bertl
(i.e. the DELAYE wants to become a DELAYD with delay control)
13:53
apurvanandan[m]
ok I will select delayd there
13:55
apurvanandan[m]
So muxing is the only option for gearing
13:57
Y|_G
left the channel
13:58
apurvanandan[m]
Bertl, rx_reset is unnconnected by default after ip generation XD
14:07
Bertl
so it can't be responsible for the reset sequence, no?
14:08
apurvanandan[m]
Bertl, but how can we find the ideal delay dynamically
14:08
apurvanandan[m]
It was written it is responsible for that
14:12
Bertl
@delay: you remember my lengthy explanations about link training? :)
14:13
Bertl
@rx_sync: well, it is neither connected to the reset input nor to the other resets, so we can rule out that it does anything about reset synchronization
14:14
Bertl
it might do other things like gating the eclk or adjusting the DQSDLLC
14:15
BAndiT1983|away
changed nick to: BAndiT1983
14:15
apurvanandan[m]
It just takes lock input from DQSDLLC nothing else
14:16
Bertl
which brings me to the question what the DQSDLLC does
14:17
Bertl
it seems to adjust the clock delay
14:17
apurvanandan[m]
Yes i remember we need to find center of eye, but how can we do that with current setup?
14:17
apurvanandan[m]
Yes , pvt variation , 90 degree shift codes
14:19
apurvanandan[m]
Or maybe rx_sync is looking after those, but I have set uddcntln to constant zero
14:19
Bertl
it is an active low signal
14:20
Bertl
so you are enabling the DQSDLLC with UDDCNTL# low
14:21
Bertl
ah, so the DQSDLLC generates a 90deg shift via the DLLDELC
14:24
apurvanandan[m]
Yupp Bertl thats the thing
14:24
Bertl
I don't think we really need that, the phase shift can be generated by the PLL as well, it just makes sense with a typical DDR memory setup
14:26
apurvanandan[m]
Okay I will try connecting rx_reset with reset of IDDR
14:26
apurvanandan[m]
Please exaplin how to use delayd here:
14:27
apurvanandan[m]
https://ibb.co/51nSvD4
14:33
Bertl
so, from the zynq (sender) perspective, there are six data channels
14:34
Bertl
each of them will generate data at the same clock rate so they will be in a constant phase relation
14:34
Bertl
each data channel has some zynq internal delay, some wire delay (length of the connection) and again some internal delay (MachXO2)
14:35
Bertl
with a little luck, you calculate those and properly adjust for them with fixed delay elements (at least up to a certain frequency and under specific conditions)
14:36
Bertl
one of the data channels has a specific pattern (the clock pattern) which is used to regenerate the source clock (again with a fixed phase relation)
14:38
Bertl
now you need to put all those delays into constraints (input on the MachXO2 side, output on the Zynq side) to get in the correct ballpark for properly receiving the data
14:38
Bertl
this will work up to 600MHz or so and might be just what is limiting your transfer at the moment
14:39
Bertl
checking different data channels independantly might give some clues here as they will have slightly different delays :)
14:39
apurvanandan[m]
But does dynamic delay comes in play, we can do this with delaye also right?
14:40
Bertl
the DELAYE is static, you can't change it once it is set
14:41
apurvanandan[m]
So are we calculating these delay and setting them ?
14:41
apurvanandan[m]
Once for all
14:41
BAndiT1983
changed nick to: BAndiT1983|away
14:41
Bertl
what about changes in temperature or power, etc
14:41
BAndiT1983|away
changed nick to: BAndiT1983
14:41
Bertl
you want to load a new bitstream?
14:42
apurvanandan[m]
So how can we calculate it inside FPGA?
14:42
Bertl
we do not calculate it, we adjust it
14:42
apurvanandan[m]
ah, the gpios?
14:43
Bertl
not required, but could be an option for testing
14:43
Bertl
as I explained a long time ago, there are several approaches to link training and thus delay adjustments
14:44
Bertl
one is to use a training pattern in regular intervals and during transmission of this pattern, the delays are adjusted to reproduce the pattern as good as possible
14:45
Bertl
another way is to use oversampling to verify the current adjustment
14:45
Bertl
e.g. with the x4 DDR, you get 8 samples of the signal at specific positions
14:46
Bertl
if your sampling is higher than the actual data rate, e.g. data comes in with 600Mbit but you sample about 1200Mbit
14:47
Bertl
then every second bit will be a transition i.e. an unstable state
14:47
Bertl
or no transition when the data doesn't change
14:47
Bertl
this additional information can be used to assert the quality of the delay adjustment
14:48
Bertl
let's say you have an alternating sequence
14:48
Bertl
01010101 (data bits)
14:48
Bertl
and you sample them as 0011001100110011
14:48
Bertl
what does that say about your sampling point? (i.e. the delay)
14:49
apurvanandan[m]
Maybe that it is aligned with edges?
14:50
Bertl
____/~~~~\____/~~~~\____/~~~~
14:50
Bertl
mark the sample points so that you get the 00110011... sequence
14:51
apurvanandan[m]
0_0/~1~1~_0_0_/~1~1~_0_0_/~1~1~
14:52
apurvanandan[m]
Like this?
14:52
Bertl
yeah, so is your sampling optimal? i.e. centered on the data?
14:53
Bertl
btw, it is more like 0___0_/~1~~~1~\_0___0_/~1~~~1~\
14:53
Bertl
because your sampling happens at regularily spaced intervals
14:55
Bertl
*regularly
14:55
Bertl
ideally you would be sampling as far away from any transition point
14:55
Bertl
so your perfect alignment (x2) would be
14:56
Bertl
\___0___/~~~1~~~\___0___/~~~1~~~\
14:56
Bertl
which in turn mens that you aim for the following x4:
14:56
apurvanandan[m]
Yeah this is clear
14:56
Bertl
X___0___X~~~1~~~X___0___X~~~1~~~X
14:57
Bertl
this also means that if your pattern is like the above
14:57
Bertl
i.e. 001100110011
14:57
Bertl
you are not perfectly aligned and you want to shift your sample point
14:58
Bertl
\_0___0_/~1~~~1~\_0___0_/~1~~~1~\
14:58
Bertl
similarily when you get a 0110011001100 pattern
14:59
Bertl
except that you want to shift in the other direction now
14:59
Bertl
so with a little statistic, you can create a locked loop which will dynamically adjust the perfect sampling point
15:00
Bertl
(note that there are a number of different approaches how to actually implement this)
15:03
apurvanandan[m]
Ok so I what I conclude : I will keep transmitting link pattern for sometime after the word alignment is right. In that time I will calculate ber multiple times with different delay values and set the finall delay value which offer statistically minimum error
15:03
Bertl
actually you should do it the other way round
15:04
Bertl
i.e. first send an alternating bit pattern
15:04
Bertl
and adjust the delays to have clean reception of this pattern
15:04
Bertl
then switch to a word pattern and do the word alignment
15:05
Bertl
note that you can do the bit alignment in a known number of steps
15:05
Bertl
so there is no need for a feedback or similar
15:05
apurvanandan[m]
So delayd offers 32 settings
15:05
Bertl
you can also use a pattern which combines bit and word pattern
15:06
Bertl
so that both alignments can be done properly
15:06
apurvanandan[m]
I can try with each of these values and find BER?
15:06
Bertl
that will probably take a long long time :)
15:07
Bertl
imagine the info screen on the Beta: "link adjusting ... please be patient, BER at 10^-13"
15:07
apurvanandan[m]
Not so precise, i can count till 10^-5 ber
15:07
apurvanandan[m]
XD lol
15:07
Bertl
what you want to do instead is to check where it is completely wrong and where it 'looks' right
15:08
Bertl
and this will give you a pattern like this:
15:08
Bertl
________|~~~~~~~|____
15:08
Bertl
where _ is just wrong and ~ means looks right
15:08
Bertl
it might be more like this actually
15:09
Bertl
________~_~_~~~~~~~_~___
15:09
Bertl
but still, it is kind of obvious where your ideal delay is, no?
15:09
apurvanandan[m]
ah this makes sense
15:10
apurvanandan[m]
lol but how do I code this , Median of first and last right value?
15:10
Bertl
certainly one approach
15:11
Bertl
note that there are a number of approaches here ... iterative ones for example
15:12
Bertl
i.e. moving two sample points till both are on the stable border
15:12
Bertl
and always using the 'midpoint' as control sample
15:13
Bertl
or just sample the correct receptions per delay value
15:13
Bertl
then the highest one wins :)
15:14
Bertl
you can also out source the calculations to the Zynq PS
15:14
apurvanandan[m]
No no not interested XD
15:15
Bertl
the first step should be 'manual' adjustment and BER testing
15:15
Bertl
e.g. use the FTDI interface to send the delay adjustments
15:15
apurvanandan[m]
Can I make direct connections of GPIOs ti my Virtex board?
15:16
Bertl
sure, works as well
15:16
apurvanandan[m]
This is really cool
15:16
apurvanandan[m]
But I need to generate the high clock
15:16
apurvanandan[m]
high speed clock
15:17
illwieckz
left the channel
15:17
apurvanandan[m]
There was one more method other than oversampling iirc
15:17
apurvanandan[m]
Was there?
15:18
Bertl
yes, ECC and dynamic adjustments based on the corrected error rate
15:18
Bertl
i.e. you can assume that you will not get a total fail when you get out of sync, instead single bits will start flipping
15:19
Bertl
by using error correction codes, you can prevent this from affecting your data
15:19
Bertl
but at the same time you can monitor the rate of the errors
15:19
Bertl
and you can do fine adjustments to the delay and observe the effect on the error rate
15:20
Bertl
always trying to minimize it of course
15:20
apurvanandan[m]
ahh, nice method
15:21
apurvanandan[m]
I am getting a feel on how much low BER can be acheived :)
15:22
Bertl
so if you go for the external delay adjustments
15:22
apurvanandan[m]
Thanks Bertl for explaining :)
15:22
Bertl
then simply do a fixed count of data transfers, e.g. 10^9 at a rate where you definitely get BER
15:23
Bertl
and then just test the BER for each delay setting
15:23
Bertl
and put that into a graph 'delay vs BER'
15:24
apurvanandan[m]
Okay!
15:24
Bertl
if you are hitting 0 BER way too often, increase the data rate :)
15:24
apurvanandan[m]
ah, great idea :)
15:28
illwieckz
joined the channel
17:48
aSobhy
Bertl should I have to assign a location for the clock or just "create_clock -period 10.000 -name sysClk -waveform {0.000 5.000} [get_ports {clk}]" would do the job?
17:49
aSobhy
because I'm getting error DRC UCIO-1 for not assigning a location to the clk port
17:49
Bertl
how should the tools know where you clock is connected?
17:50
aSobhy
"get_ports {clk}"
17:50
Bertl
so?
17:51
Bertl
that is a port 'named' 'clk' on which pin is it?
17:51
aSobhy
but the clock doesn't need pin ?!
17:52
Bertl
where does it come from?
17:53
aSobhy
I thought It will be dynamically feed the clock tree ?
17:53
Bertl
you mean, clocks come out of nowhere and just happen to be there?
17:55
aSobhy
no
17:56
Bertl
so, if you state there is a clock called sysClk with 100MHz, you need to specify where it comes from
17:57
Bertl
it could come from an internal oscillator (if available) or from an external pin (e.g. via some clock buffer)
17:58
aSobhy
But create clock will create a clock from the internal oscillator right ?
17:59
Bertl
nope
17:59
Bertl
create_clock will create a new definition for a clock network
17:59
aSobhy
Its a definition only ?
17:59
Bertl
it is purely a constraint
17:59
aSobhy
ah you said
18:00
aSobhy
how can I map that to its oscillator ?
18:01
Bertl
what FPGA are we talking about?
18:02
aSobhy
ZYNQ
18:02
Bertl
what board?
18:02
Bertl
the zynq has only a very limited internal oscillator and usually depends on external ones
18:03
aSobhy
MicroZed 7020
18:03
aSobhy
Is the clock coming from the power board ?!
18:04
aSobhy
not from the microzed board
18:04
Bertl
http://zedboard.org/sites/default/files/documentations/5276-MicroZed-HW-UG-v1-7-V1.pdf
18:04
Bertl
(same site I linked last time :)
18:06
Bertl
there is no FPGA specific clock on the MicroZed and we do not add one in the Beta
18:06
Bertl
so you want to use the fclk (from the PS) for clocking the fabric
18:09
Bertl
(see http://vserver.13thfloor.at/Stuff/AXIOM/BETA/blink_fclk/ as example)
18:15
apurvanandan[m]
Bertl, regarding documentation, Does it needs to be overall documentation with hardware references and resources or just documentaion of my code?
18:15
Bertl
the code should be self documenting :)
18:16
Bertl
so you want to document your design, the different approaches you took, the results and measurements
18:16
apurvanandan[m]
ahh, I get it
18:16
aSobhy
so I need to use ps7_stub to get my clock from it
18:17
Bertl
yes
18:17
aSobhy
and no need to use an input clk pin to the top module
18:17
aSobhy
I'll do that
18:18
Bertl
unless you have some external clock, no
18:20
aSobhy
yes I get it :)
18:23
Bertl
there is an internal configuration oscillator on the zynq
18:23
Bertl
it can be used for clocking simple designs, but it is not suitable for any high speed stuff
18:34
Bertl
off for now ... bbl
18:35
Bertl
changed nick to: bertl_oO
18:35
bertl_oO
changed nick to: Bertl_oO
19:01
apurvanandan[m]
Yes Bertl thats right, some lanes are outperforming others in terms of BER
19:03
apurvanandan[m]
With exactly same bit file
19:20
apurvanandan[m]
Bit alignment from page 6 of XAPP600 : exactly what is needed
19:20
apurvanandan[m]
*XAPP700
19:30
BAndiT1983
changed nick to: BAndiT1983|away
20:48
BAndiT1983|away
changed nick to: BAndiT1983
22:18
BAndiT1983
changed nick to: BAndiT1983|away
00:33
apurvanandan[m]
Bertl, my FT601 controller is missing 1 or 2 values per 200MBs
00:33
apurvanandan[m]
1 or 2 32 bit values
00:34
apurvanandan[m]
Or rather I had say there is problem from async fifo end
00:43
Bertl_oO
what is your data rate on both sides of the FIFO?
00:44
apurvanandan[m]
On write side we have 60 MHz 32 bit width
00:44
apurvanandan[m]
On read side we have 32 bit width at 100 MHz
00:46
apurvanandan[m]
Actually on write side we have 75 MHz in which one clock cycle has write enable zero once every 5 cycle
00:47
Bertl_oO
okay, so you are not overloading the FIFO
00:47
Bertl_oO
IIRC, your fifo is also quite deep or did you adjust that?
00:48
apurvanandan[m]
yupp
00:48
apurvanandan[m]
Yes it is 512 words deep
00:49
apurvanandan[m]
Also I should reset read pointer once in starting thats all ?
00:50
Bertl_oO
and the fifo read/FTDI is clocked by the FTDI clock, yes?
00:51
apurvanandan[m]
Sorry not 1-2 but many values are lost in chunks eg after 150MBs received 100 words are lost and again 120 MBs received correctly.
00:52
apurvanandan[m]
Yes clocked by FTDI 100MHz clock
00:53
apurvanandan[m]
Less frequently but lose occurs and in chunks
00:54
Bertl_oO
the USB bus is otherwise unused?
00:54
apurvanandan[m]
I didn't get you
00:54
apurvanandan[m]
When fifo is empty, the USB is unused
00:54
Bertl_oO
do you have anything else on the USB except for the FTDI?
00:55
apurvanandan[m]
No actually a USB Hub is attached with all jtags and usb keyboard mouse :)
00:56
Bertl_oO
so this might cause the data drops
00:56
apurvanandan[m]
mind = blown
00:56
apurvanandan[m]
Let me try that
00:56
Bertl_oO
i.e. when you get close to the total bandwidth
00:57
apurvanandan[m]
I am acheiving 300MBps bandwitdh from FT601
00:57
apurvanandan[m]
pretty close to 380 MBps
00:57
Bertl_oO
the main question is: can a drop be detected?
00:58
apurvanandan[m]
Let me try that, maybe thats not the issue