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#apertus IRC Channel Logs

2019/08/04

Timezone: UTC


00:08
Fares
left the channel
00:43
WalterZimmermann
left the channel
00:50
abeljj[m]
left the channel
02:10
aSobhy
Bertl I get lost I think its because I didn't add the part 7020
02:11
aSobhy
I searched alot but can't find how to add them
02:11
Bertl_oO
hmm?
02:11
aSobhy
I download the files
02:11
aSobhy
downloaded*
02:12
Bertl_oO
the board definition files?
02:12
aSobhy
yes
02:12
Bertl_oO
and did you unpack them in the proper location?
02:13
aSobhy
what location ?!
02:13
Bertl_oO
as described in the readme?
02:14
Bertl_oO
if you unpack the archive, there is a PDF and another archive
02:14
Bertl_oO
the pdf is title 'Install Avnet Board Definition Files in ...'
02:15
aSobhy
no their are two files only .xml
02:16
Bertl_oO
http://zedboard.org/sites/default/files/documentations/Avnet%20Zed%20Board%20Defnition%20Files.zip
02:19
aSobhy
thanks :)
02:20
aSobhy
every time you prove that I have to ask first xD
02:21
Bertl_oO
well, I gave you the link where this archive is yesterday
02:22
Bertl_oO
(not that it is hard to find with google :)
02:23
Bertl_oO
anyway, you're welcome
02:32
aSobhy
I was on that link :( and every page I opened was referring to the same link
02:45
aSobhy
how can I toggle a pin by the PIC16?
02:45
Bertl_oO
via I2C
02:47
Bertl_oO
there is a tool called pic_gpio.py
02:47
aSobhy
i2c0_bit_clr 0x22 0x15 7 sleep 0.1 i2c0_bit_set 0x22 0x15 7
02:48
aSobhy
like that
02:48
Bertl_oO
that's the GPIO extender. not the pic
02:49
Bertl_oO
i.e. wrong I2C bus
02:49
aSobhy
ah okay sorry
02:52
illwieckz
left the channel
02:55
illwieckz
joined the channel
03:57
Bertl_oO
did the script work for your purpose?
04:12
aSobhy
didn't dig through it I have an error at the bit stream generation "[DRC NSTD-1]"
04:14
Bertl_oO
unspecified I/O standard?
04:14
aSobhy
yes
04:15
Bertl_oO
well, specify the IO standard for the listed pins
04:17
aSobhy
set_property IOSTANDARD LVCMOS25 [get_ports {spi_*}]
04:17
aSobhy
like that
04:17
Bertl_oO
for example
04:18
aSobhy
OK
04:24
Bertl_oO
btw, when did you last work with the remote beta?
04:24
aSobhy
16 mins
04:25
Bertl_oO
and when was the last time you flashed one of the MachXO2s?
04:25
aSobhy
along time !
04:26
Bertl_oO
yeah, looks like ...
04:31
Bertl_oO
anyway, off to bed now ... have a good one everyone!
04:31
Bertl_oO
changed nick to: Bertl_zZ
04:34
aSobhy
nn :)
07:55
BAndiT1983|away
changed nick to: BAndiT1983
08:40
Y|_G
joined the channel
08:42
Y_|G
left the channel
09:12
Nira|away
changed nick to: Nira
11:29
apurvanandan[m]
Bertl, we can't just replicate the current system 5 times for 5 lanes as we have only 2 DQSDLL and 4 ECLKSYNC available on machXO2
11:29
apurvanandan[m]
We need to use IPexpress implementation only
11:45
BAndiT1983
changed nick to: BAndiT1983|away
11:45
Nira
changed nick to: Nira|away
12:30
Bertl_zZ
changed nick to: Bertl
12:30
Bertl
morning folks!
12:31
apurvanandan[m]
Good morning Bertl
12:31
Bertl
apurvanandan[m]: and what 'magic' do you think does IPexpress do to make it happen?
12:31
apurvanandan[m]
This is IPexpress implementation is this : https://ibb.co/D7m6N08
12:32
apurvanandan[m]
There isn't any magic about IPexpress, I am just saying we need to use everything once except the IDDR4XB
12:33
Bertl
that is kind of what I expected ...
12:34
apurvanandan[m]
Yupp, this is correct. I will go with this only.
12:34
apurvanandan[m]
Also I have a idea
12:34
Bertl
note: I still do not know what the rx_sync really does?
12:35
apurvanandan[m]
Described on page 33 of TN1203
12:37
apurvanandan[m]
It is therefore necessary to make sure all the components, such as CLKDIV and IDDR/ODDR, start with the same
12:37
apurvanandan[m]
high-speed edge clock cycle to maintain the clock domain crossing margin between ECLK and SCLK, and to avoid
12:37
apurvanandan[m]
bus bit-order scrambling due to the various delay of the reset pulse.
12:37
apurvanandan[m]
So it does reset syncronisation
12:38
Bertl
but in your schematic, the reset pin of the rx_sync is not even connected, no?
12:40
Bertl
and all the reset pins are directly conencted to your reset input
12:40
apurvanandan[m]
Basically, the rx_stop stops the eclk, and external reset is provided
12:40
apurvanandan[m]
I think there is some mistake
12:42
apurvanandan[m]
rx_reset should be joined to reset of all modules after dlldelc
12:42
Bertl
that would make a lot more sense to me :)
12:42
apurvanandan[m]
Probably this was result of code cleanup lol
12:43
Bertl
on your side?
12:43
apurvanandan[m]
Yes
12:43
Bertl
okay :)
12:43
Bertl
I'd double check with a newly IPexpress generated soft IP (i.e. create a schematic for that and compare it)
12:44
apurvanandan[m]
Bertl, I have an idea can we use 40 bits recieved from 5 channels as 4 encoded words which would result in 4 8 bits decoded words that is 32 bits :)
12:45
Bertl
sure
12:45
Bertl
but you are spreading the 8b10b codes over different channels then
12:46
Bertl
(which kind of defeats the purpose)
12:46
Bertl
i.e. you might be better off with dropping the encoding and just signalling control codes
12:46
apurvanandan[m]
So 32bits -> encode -> 40 bits -> transmit on 5 channels -> receive -> 40 bits -> decode -> 32 bits -> FTDI
12:46
apurvanandan[m]
Yes
12:48
apurvanandan[m]
Yup
12:48
Bertl
and you probably want to train the LVDS channels individually
12:49
apurvanandan[m]
Is there anyway we can make use of these ratios
12:49
Bertl
as they will have different wire lengths
12:49
Bertl
(i.e. the DELAYE wants to become a DELAYD with delay control)
12:53
apurvanandan[m]
ok I will select delayd there
12:55
apurvanandan[m]
So muxing is the only option for gearing
12:57
Y|_G
left the channel
12:58
apurvanandan[m]
Bertl, rx_reset is unnconnected by default after ip generation XD
13:07
Bertl
so it can't be responsible for the reset sequence, no?
13:08
apurvanandan[m]
Bertl, but how can we find the ideal delay dynamically
13:08
apurvanandan[m]
It was written it is responsible for that
13:12
Bertl
@delay: you remember my lengthy explanations about link training? :)
13:13
Bertl
@rx_sync: well, it is neither connected to the reset input nor to the other resets, so we can rule out that it does anything about reset synchronization
13:14
Bertl
it might do other things like gating the eclk or adjusting the DQSDLLC
13:15
BAndiT1983|away
changed nick to: BAndiT1983
13:15
apurvanandan[m]
It just takes lock input from DQSDLLC nothing else
13:16
Bertl
which brings me to the question what the DQSDLLC does
13:17
Bertl
it seems to adjust the clock delay
13:17
apurvanandan[m]
Yes i remember we need to find center of eye, but how can we do that with current setup?
13:17
apurvanandan[m]
Yes , pvt variation , 90 degree shift codes
13:19
apurvanandan[m]
Or maybe rx_sync is looking after those, but I have set uddcntln to constant zero
13:19
Bertl
it is an active low signal
13:20
Bertl
so you are enabling the DQSDLLC with UDDCNTL# low
13:21
Bertl
ah, so the DQSDLLC generates a 90deg shift via the DLLDELC
13:24
apurvanandan[m]
Yupp Bertl thats the thing
13:24
Bertl
I don't think we really need that, the phase shift can be generated by the PLL as well, it just makes sense with a typical DDR memory setup
13:26
apurvanandan[m]
Okay I will try connecting rx_reset with reset of IDDR
13:26
apurvanandan[m]
Please exaplin how to use delayd here:
13:27
apurvanandan[m]
https://ibb.co/51nSvD4
13:33
Bertl
so, from the zynq (sender) perspective, there are six data channels
13:34
Bertl
each of them will generate data at the same clock rate so they will be in a constant phase relation
13:34
Bertl
each data channel has some zynq internal delay, some wire delay (length of the connection) and again some internal delay (MachXO2)
13:35
Bertl
with a little luck, you calculate those and properly adjust for them with fixed delay elements (at least up to a certain frequency and under specific conditions)
13:36
Bertl
one of the data channels has a specific pattern (the clock pattern) which is used to regenerate the source clock (again with a fixed phase relation)
13:38
Bertl
now you need to put all those delays into constraints (input on the MachXO2 side, output on the Zynq side) to get in the correct ballpark for properly receiving the data
13:38
Bertl
this will work up to 600MHz or so and might be just what is limiting your transfer at the moment
13:39
Bertl
checking different data channels independantly might give some clues here as they will have slightly different delays :)
13:39
apurvanandan[m]
But does dynamic delay comes in play, we can do this with delaye also right?
13:40
Bertl
the DELAYE is static, you can't change it once it is set
13:41
apurvanandan[m]
So are we calculating these delay and setting them ?
13:41
apurvanandan[m]
Once for all
13:41
BAndiT1983
changed nick to: BAndiT1983|away
13:41
Bertl
what about changes in temperature or power, etc
13:41
BAndiT1983|away
changed nick to: BAndiT1983
13:41
Bertl
you want to load a new bitstream?
13:42
apurvanandan[m]
So how can we calculate it inside FPGA?
13:42
Bertl
we do not calculate it, we adjust it
13:42
apurvanandan[m]
ah, the gpios?
13:43
Bertl
not required, but could be an option for testing
13:43
Bertl
as I explained a long time ago, there are several approaches to link training and thus delay adjustments
13:44
Bertl
one is to use a training pattern in regular intervals and during transmission of this pattern, the delays are adjusted to reproduce the pattern as good as possible
13:45
Bertl
another way is to use oversampling to verify the current adjustment
13:45
Bertl
e.g. with the x4 DDR, you get 8 samples of the signal at specific positions
13:46
Bertl
if your sampling is higher than the actual data rate, e.g. data comes in with 600Mbit but you sample about 1200Mbit
13:47
Bertl
then every second bit will be a transition i.e. an unstable state
13:47
Bertl
or no transition when the data doesn't change
13:47
Bertl
this additional information can be used to assert the quality of the delay adjustment
13:48
Bertl
let's say you have an alternating sequence
13:48
Bertl
01010101 (data bits)
13:48
Bertl
and you sample them as 0011001100110011
13:48
Bertl
what does that say about your sampling point? (i.e. the delay)
13:49
apurvanandan[m]
Maybe that it is aligned with edges?
13:50
Bertl
____/~~~~\____/~~~~\____/~~~~
13:50
Bertl
mark the sample points so that you get the 00110011... sequence
13:51
apurvanandan[m]
0_0/~1~1~_0_0_/~1~1~_0_0_/~1~1~
13:52
apurvanandan[m]
Like this?
13:52
Bertl
yeah, so is your sampling optimal? i.e. centered on the data?
13:53
Bertl
btw, it is more like 0___0_/~1~~~1~\_0___0_/~1~~~1~\
13:53
Bertl
because your sampling happens at regularily spaced intervals
13:55
Bertl
*regularly
13:55
Bertl
ideally you would be sampling as far away from any transition point
13:55
Bertl
so your perfect alignment (x2) would be
13:56
Bertl
\___0___/~~~1~~~\___0___/~~~1~~~\
13:56
Bertl
which in turn mens that you aim for the following x4:
13:56
apurvanandan[m]
Yeah this is clear
13:56
Bertl
X___0___X~~~1~~~X___0___X~~~1~~~X
13:57
Bertl
this also means that if your pattern is like the above
13:57
Bertl
i.e. 001100110011
13:57
Bertl
you are not perfectly aligned and you want to shift your sample point
13:58
Bertl
\_0___0_/~1~~~1~\_0___0_/~1~~~1~\
13:58
Bertl
similarily when you get a 0110011001100 pattern
13:59
Bertl
except that you want to shift in the other direction now
13:59
Bertl
so with a little statistic, you can create a locked loop which will dynamically adjust the perfect sampling point
14:00
Bertl
(note that there are a number of different approaches how to actually implement this)
14:03
apurvanandan[m]
Ok so I what I conclude : I will keep transmitting link pattern for sometime after the word alignment is right. In that time I will calculate ber multiple times with different delay values and set the finall delay value which offer statistically minimum error
14:03
Bertl
actually you should do it the other way round
14:04
Bertl
i.e. first send an alternating bit pattern
14:04
Bertl
and adjust the delays to have clean reception of this pattern
14:04
Bertl
then switch to a word pattern and do the word alignment
14:05
Bertl
note that you can do the bit alignment in a known number of steps
14:05
Bertl
so there is no need for a feedback or similar
14:05
apurvanandan[m]
So delayd offers 32 settings
14:05
Bertl
you can also use a pattern which combines bit and word pattern
14:06
Bertl
so that both alignments can be done properly
14:06
apurvanandan[m]
I can try with each of these values and find BER?
14:06
Bertl
that will probably take a long long time :)
14:07
Bertl
imagine the info screen on the Beta: "link adjusting ... please be patient, BER at 10^-13"
14:07
apurvanandan[m]
Not so precise, i can count till 10^-5 ber
14:07
apurvanandan[m]
XD lol
14:07
Bertl
what you want to do instead is to check where it is completely wrong and where it 'looks' right
14:08
Bertl
and this will give you a pattern like this:
14:08
Bertl
________|~~~~~~~|____
14:08
Bertl
where _ is just wrong and ~ means looks right
14:08
Bertl
it might be more like this actually
14:09
Bertl
________~_~_~~~~~~~_~___
14:09
Bertl
but still, it is kind of obvious where your ideal delay is, no?
14:09
apurvanandan[m]
ah this makes sense
14:10
apurvanandan[m]
lol but how do I code this , Median of first and last right value?
14:10
Bertl
certainly one approach
14:11
Bertl
note that there are a number of approaches here ... iterative ones for example
14:12
Bertl
i.e. moving two sample points till both are on the stable border
14:12
Bertl
and always using the 'midpoint' as control sample
14:13
Bertl
or just sample the correct receptions per delay value
14:13
Bertl
then the highest one wins :)
14:14
Bertl
you can also out source the calculations to the Zynq PS
14:14
apurvanandan[m]
No no not interested XD
14:15
Bertl
the first step should be 'manual' adjustment and BER testing
14:15
Bertl
e.g. use the FTDI interface to send the delay adjustments
14:15
apurvanandan[m]
Can I make direct connections of GPIOs ti my Virtex board?
14:16
Bertl
sure, works as well
14:16
apurvanandan[m]
This is really cool
14:16
apurvanandan[m]
But I need to generate the high clock
14:16
apurvanandan[m]
high speed clock
14:17
illwieckz
left the channel
14:17
apurvanandan[m]
There was one more method other than oversampling iirc
14:17
apurvanandan[m]
Was there?
14:18
Bertl
yes, ECC and dynamic adjustments based on the corrected error rate
14:18
Bertl
i.e. you can assume that you will not get a total fail when you get out of sync, instead single bits will start flipping
14:19
Bertl
by using error correction codes, you can prevent this from affecting your data
14:19
Bertl
but at the same time you can monitor the rate of the errors
14:19
Bertl
and you can do fine adjustments to the delay and observe the effect on the error rate
14:20
Bertl
always trying to minimize it of course
14:20
apurvanandan[m]
ahh, nice method
14:21
apurvanandan[m]
I am getting a feel on how much low BER can be acheived :)
14:22
Bertl
so if you go for the external delay adjustments
14:22
apurvanandan[m]
Thanks Bertl for explaining :)
14:22
Bertl
then simply do a fixed count of data transfers, e.g. 10^9 at a rate where you definitely get BER
14:23
Bertl
and then just test the BER for each delay setting
14:23
Bertl
and put that into a graph 'delay vs BER'
14:24
apurvanandan[m]
Okay!
14:24
Bertl
if you are hitting 0 BER way too often, increase the data rate :)
14:24
apurvanandan[m]
ah, great idea :)
14:28
illwieckz
joined the channel
16:48
aSobhy
Bertl should I have to assign a location for the clock or just "create_clock -period 10.000 -name sysClk -waveform {0.000 5.000} [get_ports {clk}]" would do the job?
16:49
aSobhy
because I'm getting error DRC UCIO-1 for not assigning a location to the clk port
16:49
Bertl
how should the tools know where you clock is connected?
16:50
aSobhy
"get_ports {clk}"
16:50
Bertl
so?
16:51
Bertl
that is a port 'named' 'clk' on which pin is it?
16:51
aSobhy
but the clock doesn't need pin ?!
16:52
Bertl
where does it come from?
16:53
aSobhy
I thought It will be dynamically feed the clock tree ?
16:53
Bertl
you mean, clocks come out of nowhere and just happen to be there?
16:55
aSobhy
no
16:56
Bertl
so, if you state there is a clock called sysClk with 100MHz, you need to specify where it comes from
16:57
Bertl
it could come from an internal oscillator (if available) or from an external pin (e.g. via some clock buffer)
16:58
aSobhy
But create clock will create a clock from the internal oscillator right ?
16:59
Bertl
nope
16:59
Bertl
create_clock will create a new definition for a clock network
16:59
aSobhy
Its a definition only ?
16:59
Bertl
it is purely a constraint
16:59
aSobhy
ah you said
17:00
aSobhy
how can I map that to its oscillator ?
17:01
Bertl
what FPGA are we talking about?
17:02
aSobhy
ZYNQ
17:02
Bertl
what board?
17:02
Bertl
the zynq has only a very limited internal oscillator and usually depends on external ones
17:03
aSobhy
MicroZed 7020
17:03
aSobhy
Is the clock coming from the power board ?!
17:04
aSobhy
not from the microzed board
17:04
Bertl
http://zedboard.org/sites/default/files/documentations/5276-MicroZed-HW-UG-v1-7-V1.pdf
17:04
Bertl
(same site I linked last time :)
17:06
Bertl
there is no FPGA specific clock on the MicroZed and we do not add one in the Beta
17:06
Bertl
so you want to use the fclk (from the PS) for clocking the fabric
17:09
Bertl
(see http://vserver.13thfloor.at/Stuff/AXIOM/BETA/blink_fclk/ as example)
17:15
apurvanandan[m]
Bertl, regarding documentation, Does it needs to be overall documentation with hardware references and resources or just documentaion of my code?
17:15
Bertl
the code should be self documenting :)
17:16
Bertl
so you want to document your design, the different approaches you took, the results and measurements
17:16
apurvanandan[m]
ahh, I get it
17:16
aSobhy
so I need to use ps7_stub to get my clock from it
17:17
Bertl
yes
17:17
aSobhy
and no need to use an input clk pin to the top module
17:17
aSobhy
I'll do that
17:18
Bertl
unless you have some external clock, no
17:20
aSobhy
yes I get it :)
17:23
Bertl
there is an internal configuration oscillator on the zynq
17:23
Bertl
it can be used for clocking simple designs, but it is not suitable for any high speed stuff
17:34
Bertl
off for now ... bbl
17:35
Bertl
changed nick to: bertl_oO
17:35
bertl_oO
changed nick to: Bertl_oO
18:01
apurvanandan[m]
Yes Bertl thats right, some lanes are outperforming others in terms of BER
18:03
apurvanandan[m]
With exactly same bit file
18:20
apurvanandan[m]
Bit alignment from page 6 of XAPP600 : exactly what is needed
18:20
apurvanandan[m]
*XAPP700
18:30
BAndiT1983
changed nick to: BAndiT1983|away
19:48
BAndiT1983|away
changed nick to: BAndiT1983
21:18
BAndiT1983
changed nick to: BAndiT1983|away
23:33
apurvanandan[m]
Bertl, my FT601 controller is missing 1 or 2 values per 200MBs
23:33
apurvanandan[m]
1 or 2 32 bit values
23:34
apurvanandan[m]
Or rather I had say there is problem from async fifo end
23:43
Bertl_oO
what is your data rate on both sides of the FIFO?
23:44
apurvanandan[m]
On write side we have 60 MHz 32 bit width
23:44
apurvanandan[m]
On read side we have 32 bit width at 100 MHz
23:46
apurvanandan[m]
Actually on write side we have 75 MHz in which one clock cycle has write enable zero once every 5 cycle
23:47
Bertl_oO
okay, so you are not overloading the FIFO
23:47
Bertl_oO
IIRC, your fifo is also quite deep or did you adjust that?
23:48
apurvanandan[m]
yupp
23:48
apurvanandan[m]
Yes it is 512 words deep
23:49
apurvanandan[m]
Also I should reset read pointer once in starting thats all ?
23:50
Bertl_oO
and the fifo read/FTDI is clocked by the FTDI clock, yes?
23:51
apurvanandan[m]
Sorry not 1-2 but many values are lost in chunks eg after 150MBs received 100 words are lost and again 120 MBs received correctly.
23:52
apurvanandan[m]
Yes clocked by FTDI 100MHz clock
23:53
apurvanandan[m]
Less frequently but lose occurs and in chunks
23:54
Bertl_oO
the USB bus is otherwise unused?
23:54
apurvanandan[m]
I didn't get you
23:54
apurvanandan[m]
When fifo is empty, the USB is unused
23:54
Bertl_oO
do you have anything else on the USB except for the FTDI?
23:55
apurvanandan[m]
No actually a USB Hub is attached with all jtags and usb keyboard mouse :)
23:56
Bertl_oO
so this might cause the data drops
23:56
apurvanandan[m]
mind = blown
23:56
apurvanandan[m]
Let me try that
23:56
Bertl_oO
i.e. when you get close to the total bandwidth
23:57
apurvanandan[m]
I am acheiving 300MBps bandwitdh from FT601
23:57
apurvanandan[m]
pretty close to 380 MBps
23:57
Bertl_oO
the main question is: can a drop be detected?
23:58
apurvanandan[m]
Let me try that, maybe thats not the issue