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#apertus IRC Channel Logs

2021/06/04

Timezone: UTC


02:45
illwieckz
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illwieckz
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03:11
Bertl
off to bed now ... have a good one everyone!
03:11
Bertl
changed nick to: Bertl_zZ
06:42
se6astian
good day
09:02
Spirit532
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Spirit532
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10:33
Bertl_zZ
changed nick to: Bertl
10:33
Bertl
morning folks!
10:54
se6astian
hello!
14:49
Bertl
off for now ... bbl
14:49
Bertl
changed nick to: Bertl_oO
15:40
manav
Bertl_oO: I want to check if my understanding is correct . For the eMMC data write scenario the zync will send the command packet first and then wait for the response packet from the eMMC emulator before sending the data packets .
15:42
manav
my design i have 2 state machines my design i have 2 state machines.One that will act a eMMC emulator and the other will act as eMMC master .One that will act a eMMC slave and the other will act as eMMC master.
15:44
manav
sorry for the typo
15:46
manav
And I will buffer the commands,response,write data and read data in 4 FIFO blocks.
15:47
manav
The Zynq will communicate with the slave eMMC and the Master eMMC will then commuincate the same commands to the actual eMMC
15:48
manav
Is this the correct way forward for my design
17:32
Bertl_oO
There is no need to 'buffer' or 'transport' eMMC commands between Zynq and later MachXO2 (or whatever FPGA we decide to use in the eMMC storage module)
17:34
Bertl_oO
We can transfer data between Zynq and the eMMC controller FPGA in a much more efficient way and we definitely do not want to wait for a reply there
17:34
Bertl_oO
But the transport between the Zynq and the eMMC storage controller should not bother you at the moment
17:35
Bertl_oO
I.e. your focus should be on the Storage Controller part, in the first iteration this is the Zynq with direct access to the prototype eMMC module
17:36
Bertl_oO
Later this will be a separate FPGA on the eMMC Storage Module
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egfg
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