#apertus IRC Channel Logs

yes, please leave it on

Hey Bertl, It worked, we are able to program the RFW with our own code :D

We toggled a pin also

Now will prepare for presentation :)

I mean IRC chat.

Yeah, I will make slides. 15 min long presentation will be fine?

Okk

morning folks!

off for now ... bbl

https://github.com/kakashi-Of-Saringan/opencine/commit/78c6c8ebde8ae724310b6da443be124f34530559

What are the next steps regrading playback , optimization or bringing sliders into processing test

apurvanandan[m]: how are you?

I am fine

Presentation is almost ready, just changing a slide a bit

But didn't get the time to rehearse what I have to speak

https://docs.google.com/presentation/d/14qhVNg21O4JjeTLjCuC_IdNfXwxFWjM-F1kAMySoTxU/edit?usp=sharing

okay then, let's hear about the FT601Q then

Next Slide please

ok

Slide 3. The first point FT601Q is a high performance FTDI USB 3.0 to 32-bit wide parallel FIFO interface bridge chip with up to 5Gbps of bandwidth.

at up to 5Gbit/s?

Not this chip.

okay

On slide 4

So this is the functional description, meaning we have these subunits inside the ft601q. Most of them are somewhat electrical side of the chip. The main thing here is the FIFO protocol management unit and the USB3.0 controller. Explained on next slide.

So , as it says. USB 3.0 protocol controller is responsible for the USB 3.0 interfacing of ft601q with connected pc.

The ft601q has certain number of channels and buffer allocated to the channels. The management of this buffer and 32bit fifo interface is done by the fifo management uni

can this be changed?

The ft601q offers various configuration, some main configs are discussed.

ft245 mode is for greater compatability with usb 2.0

but at USB 3 speeds?

I searched this thing, Most probably it works with USB 3.0 also, similar to FT600 in single channel in out mode

Depending on that it distributes the buffer available in the chips ie 8KB

On slide 7

*handling

YesBertl

Ok

In this condition, the session underrun is handled by sending the data in the fifo to the usb 3.0 host

Master is the FIFO bus master ie the fpga

okay, so that is something done _outside_ the FT601

Then there are the notification pipes, they are just a feedback of the amount of data from the master to the connected pc. I don't find them that useful but it is a config so it is here.

The main thing

Firstly,all the *_N are active low

TXE_N is a optional signal, states that the master fifo idle status is valid or not

i is counter for the 4 channels

well, maybe :)

On slide 9

With each configuration available

You can have a look at that later

On slide 10

On slide 11

And also for commanding the slave ie ft601q using the BE and DATA[7:0]

On slide 12

I think , when the master makes the bus idle it asserts 1s and then the fifo status is checked by data bus. But I will confirm that later

As we are dealing with large amounts of data , we need to maximise the performance of ft601q as per our needs

The formula for efficiency is given with each timing variable marked in the bottom diagram.

why is multi channel data rate higher than single channel?

well, to me it looks like we have overhead for switching between the channels

so I would assume that I can supply a single channel with almost 400MB/s (limited by the clock rate)

which will actually steal some data cycles

Looks like when we already are using 4 channels then it may be benficial. But a single channel with perform better ( see on slide 13).

on slide 13, the unlabeled axis at the bottom is the idle cycles per second?

They haven't written the unit anywhere on the documentation

On slide 15 : THANK YOU :)

:)

I was unprepared, otherwise it would have been concise

now 120 or 320 idle cycles there should not matter at all

at 120 [whatever] we already have lost 10% of our total bandwidth

aSobhy: you around?

I am checking just a sec

Bertl: You can go through page 5 of the 6th reference link in slide 14

fair enough, want to do a presentation next week?

for what topic

for what topic ?

The time of meeting is also wasted

its very interesting to follow from my perspective at least

also didn't expect it to last one and a half hour :)

ok Bertl JTAG next week :)

I would like you speaking and we listening.

apurvanandan[m], i think gsoc work a bit different and students have to propose

so back to the interesting aspects ...

I think the timing diagram makes it obvious that we want to avoid everything but data cycles to maximize throughput

an interesting aspect is that we can do bidirectional stuff on USB 3.0 with only the bus turn around (and maybe a command?) cycle

I'm also not sure what the difference between the FT245 and FT601 mode is when operating with one channel

let's assume we can transfer 4k in one go

let's say we need 4 cycles for this, which is about 0.1% of the total bandwidth

maybe _florent__ has some input on this, but not sure he is around

which brings the question, why would there be 120-320 idle cycles each 4k data package?

anyway, we won't solve that right now (by contemplation) we need to do some test there

Yes sorry for delay

well, I guess you managed to design, build, convert, upload and test code on one of the MachXO2s :)

yes the RFW that we were on it yesterday

is the code somewhere online?

it was togling a bit(we choose the CLK) and we checked it with eye as we type pic_gpio multiple of time and see it toggling

okay

of course! :)

Now we need to dig a little more, and get this thing from emio of zynq

and also on RFE

Ohh yes, I forgot, will do tomorrow

I will start working on the ft601 controller also.

good, check with _florent__ when he's around, might have some tips ready

Will try to cover up

okay, next meeting next week same time?

we also should probably do a session on the weekend with the remote Beta

great, so you did get the notification, excellent

okay then, anything else, feel free to contact me/us anytime

can I ask If I'll recive some kits soon ?

<Bertl "as explained, at the moment, the"> Bertl: Am I required to give presentation next week?

Ok Thanks! Good night!

you will certainly get something sooner or later, no worries

troubles*

it's not my task to tell you every step, in fact it's your task to provide me with information how you will proceed to solve the main goal of the gsoc task, please refer to your proposal

just at the moment it is easier for us to maintain it and if something goes terribly wrong, replace it :)