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| 05:18 | Bertl_oO | off to bed now ... have a good one everyone!
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| 07:51 | daFred | Francky: regarding the Axiom beta lensmount you can find the files on https://github.com/apertus-open-source-cinema/beta-hardware/tree/master/Enclosure/Skeleton_E-mount At the moment we use a 10mm of the shelf macro extension tube. You can find them on the web. I thing this is the easiest DIY way to go. So there is just this one part to be costom made at the moment
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| 07:53 | daFred | If you find a "standard" of the shelf part as a replacement we wold be very happy :-)). Please let us know...
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| 07:54 | comradekingu | Replacement for?
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| 07:56 | daFred | replacement for the custom made lensmount adapter to the image sensor...
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| 07:59 | comradekingu | Maybe the image-sensor maker has some?
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| 08:21 | se6astian | good morning
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| 11:26 | Francky | hi all
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| 11:28 | se6astian | hi there
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| 11:29 | Francky | hi sebastian
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| 11:29 | Francky | thanks daFred for the lens holder plans
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| 11:34 | Francky | has someone some news about beta tests ?
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| 11:53 | Bertl_zZ | changed nick to: Bertl
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| 11:53 | Bertl | morning folks!
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| 11:55 | Francky | hi Bertl. I was asking about beta news :)
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| 11:57 | Bertl | We have updated the designs and fixed all the known bugs there
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| 11:57 | Bertl | Beta itself is working as expected, nothing really new there atm
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| 11:59 | Bertl | First snapshots have been uploaded, we are working on an HDMI output workaround
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| 12:06 | Bertl | (till we have a proper HDMI out module)
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| 12:18 | Francky | great !
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| 12:19 | Francky | will you build a cmv2000 sensor board to have a "low cost" but "1080p" capable camera ?
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| 12:19 | Bertl | yes, CMV2k/4k is planned
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| 12:20 | Francky | i might be interested in this version because of the high proce of the cmv12k
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| 12:24 | Francky | i have a very alpha version of a zynq program (fpga + script linux) that send 32bits number throught lvds lines, receive them and compare to sended values
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| 12:24 | Francky | use emio to inform linux if received data is correct or not
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| 12:24 | Francky | and write in memory the received frequency
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| 12:25 | Francky | is something intersted for you ?
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| 12:25 | Francky | i admit that i make the memory write to try it. I think i don't use correctly but it is working well
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| 12:30 | Bertl | sounds good, maybe upload it somewhere? (e.g. github)
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| 12:31 | Francky | you need to know that it is not as good as your code, but don't forget that i am beginner :)
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| 12:35 | Bertl | ugly code can be fixed :)
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| 12:55 | Francky | is it open here : https://github.com/FranckyCam/Zynq
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| 12:55 | Francky | ?
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| 13:09 | Bertl | ah, excellent! thanks!
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| 13:11 | Francky | long time ago we spoke about configuration of the pl part throught spi by the ps part, do you remember or did i understant wrong ?
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| 13:12 | Francky | for the moment i only use emio to set reset and dataenable signal in the ps side
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| 13:12 | Francky | then the pl side give emio to say if 8bits words are correct or not (4 emio) and write into memory to say the received frequency
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| 13:13 | Francky | i imagine that if i want to share data throught a spi bus, i wiil need to build a spi receiver in the pl side in vhdl right ?
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| 13:23 | Bertl | yes, the "idea" was to have some kind of simple (up to 3?) wire interface to control source and sink
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| 13:24 | Bertl | the main purpose would be to allow for bandwidth tests with "simple" FPGAs which do not have memory interfaces or EMIO
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| 13:24 | Francky | ok
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| 13:24 | Bertl | e.g. ZYNQ connects to Cyclone
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| 13:25 | Bertl | it is hard to get the data from the cyclone if you do not have some kind of simple interface to talk to it
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| 13:28 | Bertl | and did you do some actual bandwidth tests with your code? i.e. what data rates did you achieve and how is the BER?
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| 13:31 | Francky | i make all my tests at 200MHz (bit clock) = 25MHz word clock (4 parrallell lvds lines 8bits)
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| 13:31 | Francky | i also count the error in the code and i write it into shared memory to be able to watch it in linux
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| 13:32 | Francky | and there is a small number of error at the begining (time to synchronise receiver to sender)
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| 13:32 | Francky | and then no more errors
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| 13:50 | Bertl | maybe try a higher frequency then, something around 1GHz for the bit clock for example?
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| 13:54 | Francky | it doesn't work at 400MHz for now... :)
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| 14:27 | Bertl | any idea why?
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| 14:40 | Francky | no
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| 14:40 | Francky | timing report seems to be good
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| 15:33 | Francky | time to go ! bye !
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| 15:47 | se6astian | me too, time to leave the AXIOM offices
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| 15:47 | se6astian | which are slowly becoming quite nice btw :)
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| 15:47 | se6astian | we will report once they look, presentable....
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| 16:11 | Bertl | off for now ... bbl
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| 21:16 | se6astian | good night
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