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#apertus IRC Channel Logs

2015/05/04

Timezone: UTC


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06:18
Bertl_oO
off to bed now ... have a good one everyone!
06:18
Bertl_oO
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08:51
daFred
Francky: regarding the Axiom beta lensmount you can find the files on https://github.com/apertus-open-source-cinema/beta-hardware/tree/master/Enclosure/Skeleton_E-mount At the moment we use a 10mm of the shelf macro extension tube. You can find them on the web. I thing this is the easiest DIY way to go. So there is just this one part to be costom made at the moment
08:53
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08:53
daFred
If you find a "standard" of the shelf part as a replacement we wold be very happy :-)). Please let us know...
08:54
comradekingu
Replacement for?
08:56
daFred
replacement for the custom made lensmount adapter to the image sensor...
08:59
comradekingu
Maybe the image-sensor maker has some?
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se6astian|away
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09:21
se6astian
good morning
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cbohnens|away
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Francky
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12:26
Francky
hi all
12:28
se6astian
hi there
12:29
Francky
hi sebastian
12:29
Francky
thanks daFred for the lens holder plans
12:34
Francky
has someone some news about beta tests ?
12:53
Bertl_zZ
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12:53
Bertl
morning folks!
12:55
Francky
hi Bertl. I was asking about beta news :)
12:56
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12:57
Bertl
We have updated the designs and fixed all the known bugs there
12:57
Bertl
Beta itself is working as expected, nothing really new there atm
12:57
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12:59
Bertl
First snapshots have been uploaded, we are working on an HDMI output workaround
13:06
Bertl
(till we have a proper HDMI out module)
13:18
Francky
great !
13:19
Francky
will you build a cmv2000 sensor board to have a "low cost" but "1080p" capable camera ?
13:19
Bertl
yes, CMV2k/4k is planned
13:20
Francky
i might be interested in this version because of the high proce of the cmv12k
13:24
niemand
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13:24
Francky
i have a very alpha version of a zynq program (fpga + script linux) that send 32bits number throught lvds lines, receive them and compare to sended values
13:24
Francky
use emio to inform linux if received data is correct or not
13:24
Francky
and write in memory the received frequency
13:25
Francky
is something intersted for you ?
13:25
Francky
i admit that i make the memory write to try it. I think i don't use correctly but it is working well
13:30
Bertl
sounds good, maybe upload it somewhere? (e.g. github)
13:31
Francky
you need to know that it is not as good as your code, but don't forget that i am beginner :)
13:35
Bertl
ugly code can be fixed :)
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13:55
Francky
is it open here : https://github.com/FranckyCam/Zynq
13:55
Francky
?
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14:09
Bertl
ah, excellent! thanks!
14:11
Francky
long time ago we spoke about configuration of the pl part throught spi by the ps part, do you remember or did i understant wrong ?
14:12
Francky
for the moment i only use emio to set reset and dataenable signal in the ps side
14:12
Francky
then the pl side give emio to say if 8bits words are correct or not (4 emio) and write into memory to say the received frequency
14:13
Francky
i imagine that if i want to share data throught a spi bus, i wiil need to build a spi receiver in the pl side in vhdl right ?
14:23
Bertl
yes, the "idea" was to have some kind of simple (up to 3?) wire interface to control source and sink
14:24
Bertl
the main purpose would be to allow for bandwidth tests with "simple" FPGAs which do not have memory interfaces or EMIO
14:24
Francky
ok
14:24
Bertl
e.g. ZYNQ connects to Cyclone
14:25
Bertl
it is hard to get the data from the cyclone if you do not have some kind of simple interface to talk to it
14:28
Bertl
and did you do some actual bandwidth tests with your code? i.e. what data rates did you achieve and how is the BER?
14:31
Francky
i make all my tests at 200MHz (bit clock) = 25MHz word clock (4 parrallell lvds lines 8bits)
14:31
Francky
i also count the error in the code and i write it into shared memory to be able to watch it in linux
14:32
Francky
and there is a small number of error at the begining (time to synchronise receiver to sender)
14:32
Francky
and then no more errors
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masplund|away
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14:50
Bertl
maybe try a higher frequency then, something around 1GHz for the bit clock for example?
14:54
Francky
it doesn't work at 400MHz for now... :)
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Bertl
any idea why?
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15:40
Francky
no
15:40
Francky
timing report seems to be good
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jorom
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fsteinel_
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16:33
Francky
time to go ! bye !
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se6astian
me too, time to leave the AXIOM offices
16:47
se6astian
which are slowly becoming quite nice btw :)
16:47
se6astian
we will report once they look, presentable....
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se6astian
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17:11
Bertl
off for now ... bbl
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Bertl
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se6astian
good night
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