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#apertus IRC Channel Logs

2019/03/04

Timezone: UTC


01:36
futarisIRCcloud
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02:55
Bertl
off to bed now ... have a good one everyone!
02:55
Bertl
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RexOrCine
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BAndiT1983|away
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BAndiT1983
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se6astian|away
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09:25
futarisIRCcloud
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10:21
Bertl_zZ
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10:21
Bertl
morning folks!
10:22
siddhantsahu
Morning Bertl
10:22
Bertl
how's it going? everything fine?
10:23
siddhantsahu
Yes everything good.
10:23
siddhantsahu
Just had one doubt
10:28
se6astian
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10:34
virtuous
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11:21
virtuous
Hello everyone, I am working on USB Module Gear work (T885), but I had one doubt, as the page says that we are supposed to know verilog for it.. but in the challenge task T871 it has been told to "adhere to the VHDL coding syle"? So which one should we use?
11:24
Bertl
Hello virtuous!
11:24
Bertl
for the challenge task, which is VHDL, you definitely need to use VHDL
11:25
Bertl
for the gearwork task, it really depends on your preference, what tools you want to use, etc
11:31
siddhantsahu
Bertl: Regarding the C++ challenge (T872), first converting 12 bits to 8bits and then Debayer? Or first seperate channels(12 bits) and Debayer and then convert from 12 bits to 8bits? Which one I need to do?
11:32
siddhantsahu
Will Debayering while pixel values are 12 bits is better than at 8 bits?
11:33
Bertl
the task itself leaves that open to you ... naturally it would make more sense to debayer the 12bit data before converting it to 8bit
11:33
Bertl
s/open/up/
11:34
siddhantsahu
Yes I was also thinking the same
11:34
siddhantsahu
The task description was a bit confusing.
11:35
Bertl
that is very similar to real world requirements though :)
11:36
Bertl
i.e. decisions need to be made and/or more information needs to be collected
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11:37
se6astian|away
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virtuous
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11:38
siddhantsahu
Yes
11:38
siddhantsahu
Bertl: pl check your email
12:28
Bertl
So you would like to do a custom task for GSoC 2019, yes?
12:28
Bertl
in which case your first step is to create such a task including detailed description on the lab
12:29
Bertl
we will then assign challenge tasks to it as we see fit
12:33
siddhantsahu
Bertl: Okay, Will do it
12:36
se6astian
please put your custom idea/task into the misc section of the workboard
12:37
Bertl
(it should end up there by default)
12:37
siddhantsahu
se6astian: Will add that to the misc section as well
12:38
se6astian
thanks
12:39
se6astian
siddhantsahu: note that the goal for recording footage with the AXIOM Beta is to store raw data - without any whitebalancing applied
12:40
se6astian
but there is also the option to use the live output of the camera over HDMI (currenty) and SDI (soon)
12:40
se6astian
for which case whitebalancing options should be very helpful
12:41
se6astian
for preview and as metadata the whitebalace information is of course also useful for the raw recording
12:41
siddhantsahu
Yes for preview it can be helpful
12:41
se6astian
and you proposed it also for post processing in open cine so that is a good match as well
12:43
siddhantsahu
se6astian: Yes users can use the automatic white balance button in OpenCine on the imported RAW footage from AXIOM Beta
12:44
siddhantsahu
or any other RAW file after the task (T673) "Frameserving capabilities for OpenCine"
12:44
se6astian
the computing time values from the paper are related to a rather prowerful PC though: "The training and test time weremeasured on a PC with Intel Xeon 3.5GHz CPU using Mat-lab 2010."
12:44
se6astian
keep in mind the AXIOM Beta only has 2x ARM cores running at 800mhz each
12:45
siddhantsahu
Yes I am aware of the hardware of AXIOM Beta
12:45
se6astian
great
12:45
se6astian
any questions?
12:46
siddhantsahu
Maybe some faster algorithm for preview in AXIOM Beta if it doesn't work out.
12:47
siddhantsahu
Using this algorithm in OpenCine is fine. Is n't it?
12:49
Bertl
probably, but check with BAndiT1983|away when he comes back
12:51
se6astian
opencine is meant to run on a PC so I guess yes, but as Bertl suggested best check with BAndiT1983
12:54
niemand
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13:02
siddhantsahu
Will check with BAndiT1983|away when he is online
13:33
shivamgoyal
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13:56
Bertl
off for now ... bbl
13:56
Bertl
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niemand
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15:00
shivamgoyal
I have completed T1140 C challenge
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16:01
se6astian
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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se6astian|away
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BAndiT1983
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19:54
dante2608_
Hi everyone, my name is Dat Tran and I'm very interested in participating in GSoC this year. I have one question related to FPGA challenge. Do I have to finish all of them or just one is enough ?
19:54
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19:59
Bertl_oO
Hey dante2608!
19:59
Bertl_oO
as the challenge description says: "at least one" ...
20:00
Bertl_oO
in general it is preferable if you do one task well instead of several so-so
20:01
Bertl_oO
you also might want to get a proper IRC client instead of the web client :)
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22:00
se6astian
off to bed
22:00
se6astian
good night
22:00
se6astian
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BAndiT1983|away
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RexOrCine|away
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BAndiT1983
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