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| 02:55 | Bertl | off to bed now ... have a good one everyone!
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| 10:21 | Bertl | morning folks!
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| 10:22 | siddhantsahu | Morning Bertl
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| 10:22 | Bertl | how's it going? everything fine?
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| 10:23 | siddhantsahu | Yes everything good.
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| 10:23 | siddhantsahu | Just had one doubt
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| 11:21 | virtuous | Hello everyone, I am working on USB Module Gear work (T885), but I had one doubt, as the page says that we are supposed to know verilog for it.. but in the challenge task T871 it has been told to "adhere to the VHDL coding syle"? So which one should we use?
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| 11:24 | Bertl | Hello virtuous!
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| 11:24 | Bertl | for the challenge task, which is VHDL, you definitely need to use VHDL
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| 11:25 | Bertl | for the gearwork task, it really depends on your preference, what tools you want to use, etc
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| 11:31 | siddhantsahu | Bertl: Regarding the C++ challenge (T872), first converting 12 bits to 8bits and then Debayer? Or first seperate channels(12 bits) and Debayer and then convert from 12 bits to 8bits? Which one I need to do?
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| 11:32 | siddhantsahu | Will Debayering while pixel values are 12 bits is better than at 8 bits?
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| 11:33 | Bertl | the task itself leaves that open to you ... naturally it would make more sense to debayer the 12bit data before converting it to 8bit
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| 11:33 | Bertl | s/open/up/
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| 11:34 | siddhantsahu | Yes I was also thinking the same
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| 11:34 | siddhantsahu | The task description was a bit confusing.
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| 11:35 | Bertl | that is very similar to real world requirements though :)
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| 11:36 | Bertl | i.e. decisions need to be made and/or more information needs to be collected
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| 11:38 | siddhantsahu | Yes
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| 11:38 | siddhantsahu | Bertl: pl check your email
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| 12:28 | Bertl | So you would like to do a custom task for GSoC 2019, yes?
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| 12:28 | Bertl | in which case your first step is to create such a task including detailed description on the lab
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| 12:29 | Bertl | we will then assign challenge tasks to it as we see fit
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| 12:33 | siddhantsahu | Bertl: Okay, Will do it
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| 12:36 | se6astian | please put your custom idea/task into the misc section of the workboard
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| 12:37 | Bertl | (it should end up there by default)
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| 12:37 | siddhantsahu | se6astian: Will add that to the misc section as well
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| 12:38 | se6astian | thanks
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| 12:39 | se6astian | siddhantsahu: note that the goal for recording footage with the AXIOM Beta is to store raw data - without any whitebalancing applied
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| 12:40 | se6astian | but there is also the option to use the live output of the camera over HDMI (currenty) and SDI (soon)
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| 12:40 | se6astian | for which case whitebalancing options should be very helpful
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| 12:41 | se6astian | for preview and as metadata the whitebalace information is of course also useful for the raw recording
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| 12:41 | siddhantsahu | Yes for preview it can be helpful
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| 12:41 | se6astian | and you proposed it also for post processing in open cine so that is a good match as well
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| 12:43 | siddhantsahu | se6astian: Yes users can use the automatic white balance button in OpenCine on the imported RAW footage from AXIOM Beta
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| 12:44 | siddhantsahu | or any other RAW file after the task (T673) "Frameserving capabilities for OpenCine"
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| 12:44 | se6astian | the computing time values from the paper are related to a rather prowerful PC though: "The training and test time weremeasured on a PC with Intel Xeon 3.5GHz CPU using Mat-lab 2010."
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| 12:44 | se6astian | keep in mind the AXIOM Beta only has 2x ARM cores running at 800mhz each
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| 12:45 | siddhantsahu | Yes I am aware of the hardware of AXIOM Beta
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| 12:45 | se6astian | great
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| 12:45 | se6astian | any questions?
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| 12:46 | siddhantsahu | Maybe some faster algorithm for preview in AXIOM Beta if it doesn't work out.
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| 12:47 | siddhantsahu | Using this algorithm in OpenCine is fine. Is n't it?
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| 12:49 | Bertl | probably, but check with BAndiT1983|away when he comes back
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| 12:51 | se6astian | opencine is meant to run on a PC so I guess yes, but as Bertl suggested best check with BAndiT1983
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| 13:02 | siddhantsahu | Will check with BAndiT1983|away when he is online
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| 13:56 | Bertl | off for now ... bbl
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| 15:00 | shivamgoyal | I have completed T1140 C challenge
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| 19:54 | dante2608_ | Hi everyone, my name is Dat Tran and I'm very interested in participating in GSoC this year. I have one question related to FPGA challenge. Do I have to finish all of them or just one is enough ?
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| 19:59 | Bertl_oO | Hey dante2608!
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| 19:59 | Bertl_oO | as the challenge description says: "at least one" ...
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| 20:00 | Bertl_oO | in general it is preferable if you do one task well instead of several so-so
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| 20:01 | Bertl_oO | you also might want to get a proper IRC client instead of the web client :)
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| 22:00 | se6astian | off to bed
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| 22:00 | se6astian | good night
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