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#apertus IRC Channel Logs

2014/01/04

Timezone: UTC


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Bertl
off to bed now ... have a good one everyone!
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14:25
danhanes
Hello everyone - can someone (Bertl ?) familiar with the FPGA code give me an overview of the PL architecture ?
14:27
se6astian
Hi danhanes
14:27
se6astian
Bertl, should be here soon
14:28
se6astian
probably in an hour or so
14:28
danhanes
Hello Sebastian, thanks - I'm new here, Bertl and I spoke a week or so ago. I am trying to come up to speed on the FPGA code
14:42
se6astian
very good, welcome!
14:42
se6astian
is there anything I can help you with/answer in the meantime
14:43
danhanes
I finally got Vivado running, and have been looking at the vhd source.
14:43
danhanes
I can't seem to put the whole picture together in my head yhet
14:44
danhanes
I guess a high-level overview of the processing flow, PL to PC, would help
14:44
se6astian
I see, well I wont be any help there I am afraid but Bertl will :)
14:44
danhanes
Thanks - I fear the learning curve will be steep for me. But great work you guys are doing. Hope I can contribute.
14:45
se6astian
Thanks, yes would be great!
14:45
se6astian
ok time to go to the supermarket
14:45
se6astian
see you later
16:06
Bertl
morning everyone!
16:10
Bertl
danhanes: high level design atm is this
16:13
danhanes
morning Bertl - I think I missed something
16:17
Bertl
SERDES blocks to deserialize the LVDS input from the CMV12k, data rearrangement and buffering (chopper, fifo) to reorder and cross clock domain, high performance AXI writer to burst the data into PS memory
16:20
danhanes
That helps - I'm trying to follow the flow through the source files. Moving slowly.
16:20
Bertl
on the other side we got a high performance AXI reader which collects data for HDMI out
16:21
Bertl
then there is a 3x3+3 LUT based nonlinear matrix multiplication
16:21
Bertl
a scan generator which creates the HDMI timing and outputs the image data
16:22
danhanes
debayering, FPN ?
16:23
Bertl
in addition to that there are several AXI interfaces to control stuff, like the CMV SPI register, the delay register, a file register and a lut register
16:23
Bertl
debayering is done implicitely as we simply take the R, G, B channel and feed it into the matrix
16:24
Bertl
the HDMI image is 2 times smaller than the source, so no interpolation should be required
16:24
Bertl
(but in theory we could do that step before the matrix
16:24
Bertl
)
16:25
Bertl
FPN is not done yet, but is planned at the reader stage, i.e. we have enough readers working to feed FPN correction data as well
16:28
danhanes
I don't understand the "reader stage" term
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16:51
Bertl
we are using the HP AXI slave ports to write/read from DDR memory
16:51
Bertl
i.e. both reader/writer consist of an address generator and a data stream
16:52
danhanes
got it.
16:53
Bertl
we can have up to 4 independant writer/reader active
16:53
Bertl
they won't be able to work at full speed when all are enabled, but the troughput should be sufficient for our purpose (according to tests)
16:54
Bertl
the cmv_io design uses two writers to burst the sensor data to memory
16:54
Bertl
in cmv_io2 I already reduced that to a single writer which works perfectly fine
16:55
Bertl
(writer was somewhat improved/streamlined)
16:56
danhanes
glad to see the performance is there
16:57
Bertl
is that what you had in mind regarding big picture?
16:58
danhanes
Yes, very much - thanks. It will take me a while to get familiar with all of the source files & signal names
16:58
danhanes
Are you using the Vivado IDE, or Tcl
16:58
Bertl
tcl, no IDE, but vivado 1013.4 atm
16:59
Bertl
2013.4 even :)
16:59
danhanes
A millenium can make a big difference in the tech world
17:00
Bertl
yes, although the tools sometimes feel more like last century :)
17:01
danhanes
Aye, I've got 2013.4 working, and am trying to use the IDE. Yuk.
17:10
Bertl
yes, I tried to use the IDE in the beginning, but it isn't really intuitive and rather complicated to convince to do what I want
17:10
Bertl
I only use it for viewing (i.e. some simulation, floorplanning and so)
17:10
danhanes
tcl, another skillset for me to dust off
17:11
Bertl
well, the provided scripts (in my code) basically do all the required steps
17:11
danhanes
thank goodness
17:12
Bertl
there is no dependency tracking or modularization yet, as the documentation for this was almost non existant when I started half year ago
17:12
Bertl
but I have some ideas how to improve on that
17:14
danhanes
I've been going through your code. Amazing amount done so quickly. Code is easy to read - juts a lot for me to assimilate.
17:14
Bertl
thanks! appreciated!
17:15
Bertl
don't hold back if you see something suspicious. do not forget I'm quite new to FPGA programming :)
17:16
danhanes
you're way ahead of me. I hope I can be useful in a few weeks. I need to stay out of the critical path for a while
17:26
Bertl
okay, just pushed the cmv_io2 code to master
17:26
Bertl
(was in the other branch before and not completely up-to-date)
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danhanes
Bertl: Thank you very much for the enlightenment. I grabbed your push, more light reading :)
17:45
danhanes
Time to do some errands ..
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Bertl
hey philippej! how's going?
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