#apertus IRC Channel Logs

Hello everyone - can someone (Bertl ?) familiar with the FPGA code give me an overview of the PL architecture ?

Bertl, should be here soon

Hello Sebastian, thanks - I'm new here, Bertl and I spoke a week or so ago. I am trying to come up to speed on the FPGA code

is there anything I can help you with/answer in the meantime

I can't seem to put the whole picture together in my head yhet

I see, well I wont be any help there I am afraid but Bertl will :)

Thanks, yes would be great!

see you later

danhanes: high level design atm is this

SERDES blocks to deserialize the LVDS input from the CMV12k, data rearrangement and buffering (chopper, fifo) to reorder and cross clock domain, high performance AXI writer to burst the data into PS memory

on the other side we got a high performance AXI reader which collects data for HDMI out

a scan generator which creates the HDMI timing and outputs the image data

in addition to that there are several AXI interfaces to control stuff, like the CMV SPI register, the delay register, a file register and a lut register

the HDMI image is 2 times smaller than the source, so no interpolation should be required

)

I don't understand the "reader stage" term

we are using the HP AXI slave ports to write/read from DDR memory

got it.

they won't be able to work at full speed when all are enabled, but the troughput should be sufficient for our purpose (according to tests)

in cmv_io2 I already reduced that to a single writer which works perfectly fine

glad to see the performance is there

Yes, very much - thanks. It will take me a while to get familiar with all of the source files & signal names

tcl, no IDE, but vivado 1013.4 atm

A millenium can make a big difference in the tech world

Aye, I've got 2013.4 working, and am trying to use the IDE. Yuk.

I only use it for viewing (i.e. some simulation, floorplanning and so)

well, the provided scripts (in my code) basically do all the required steps

there is no dependency tracking or modularization yet, as the documentation for this was almost non existant when I started half year ago

I've been going through your code. Amazing amount done so quickly. Code is easy to read - juts a lot for me to assimilate.

don't hold back if you see something suspicious. do not forget I'm quite new to FPGA programming :)

okay, just pushed the cmv_io2 code to master

Time to do some errands ..