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#apertus IRC Channel Logs

2019/08/03

Timezone: UTC


00:52
aSobhy
Bertl where you set the Directory in "vivado.tcl" ?
00:53
Bertl
in the existing sources, the current directory is assumed
00:53
Bertl
(cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
00:54
Bertl
will build in build.vivado subdirectory
00:57
aSobhy
I searched It sets the directory from the where it typed that command but on my side don't
00:58
aSobhy
It holds at the default path : C:/Users/Abd-ElRhman/AppData/Roaming/Xilinx/
01:00
aSobhy
I asked to see If their is a way to set the directory by command
01:01
aSobhy
also "set origin_dir 'path' " didn't work
01:01
Bertl
try setting 'DIRECTORY'
01:02
apurvanandan[m]
Bertl how de we remove negative slack in timing ananlysis
01:02
Bertl
i.e. set_property DIRECTORY [current_project] ...
01:03
Bertl
apurvanandan[m]: please share the timing path
01:04
Bertl
negative slack usually arises from either excessive path delay or from clock skew
01:05
apurvanandan[m]
How can I share it here?
01:06
Bertl
pastebin?
01:06
apurvanandan[m]
The trace reports right?
01:07
Bertl
well, specifically the timing path for one (or more) of the problematic ones (with negative slack)
01:07
Bertl
you can also commit/upload the project and I'll check for myself
01:08
apurvanandan[m]
https://pastebin.com/u8Kk8ixH
01:08
apurvanandan[m]
Ok, doing that
01:08
Bertl
the paste is rather unreadable btw :)
01:09
apurvanandan[m]
Yeah, don't know why formatting got lost
01:09
aSobhy
no It didn't accept it
01:11
Bertl
what exactly is the problem at the moment?
01:12
apurvanandan[m]
https://github.com/apurvanandan1997/BER_mesurement_x1
01:12
apurvanandan[m]
Sorry I am using GUI tools, no makefile rightnow
01:14
Bertl
so how do I build it?
01:14
apurvanandan[m]
Please teach me also how to analyze timing issues
01:15
apurvanandan[m]
Do you have Diamond 3?
01:15
Bertl
3.11
01:16
apurvanandan[m]
Open the ber_measure.ldf in proj folder from open project in Diamond
01:16
apurvanandan[m]
*Please
01:18
aSobhy
I found a way :)
01:21
Bertl
apurvanandan[m]: okay, then?
01:21
Bertl
aSobhy: excellent! let's hear!
01:22
apurvanandan[m]
Generate bitsream from process, then please go to timing analysis view from tools menu
01:22
Bertl
there is no 'Generate bitsream' under 'Process'
01:25
apurvanandan[m]
Above the console there are three tabs, file list, process, herarchy
01:25
apurvanandan[m]
It is in process tab
01:29
Bertl
http://vserver.13thfloor.at/Stuff/GSoC2019/apurva_diamond.jpg
01:30
apurvanandan[m]
Yes the bitsream file under export files
01:30
apurvanandan[m]
Please double click on that
01:32
apurvanandan[m]
After that you want to go to Tools menu above in menu bar, then timing analysis view option
01:34
Bertl
not sure what it is doing right now, spinning on 'Export Files' atm
01:35
apurvanandan[m]
Yes, once it finish we can see timing analysis from the tools menu
01:41
Bertl
so how long is it supposed to work on the Bitstream File?
01:42
apurvanandan[m]
few seconds
01:42
apurvanandan[m]
:/
01:43
Bertl
http://vserver.13thfloor.at/Stuff/GSoC2019/apurva_diamond2.jpg
01:43
Bertl
it is in this state for quite some time now
01:44
Bertl
(no output, nothing, just spinning)
01:44
apurvanandan[m]
Nevermind, stop that process. Place and route is required only for timing option there
01:45
apurvanandan[m]
Rightclick and stop
01:45
Bertl
done
01:45
apurvanandan[m]
:)
01:46
Bertl
when I select Process -> Timing view
01:46
Bertl
diamond segfaults
01:47
apurvanandan[m]
Tools -> Timing Analysis View right?
01:47
Bertl
yep, sorry, Tools
01:47
Bertl
Use of deprecated SAXv1 function comment
01:47
Bertl
Segmentation fault (core dumped)
01:47
apurvanandan[m]
:/ Okay please wait I am sending the report by some means
01:48
Bertl
how about you switch the project to commandline build
01:48
Bertl
that works just fine and doesn't require messing with the GUI
01:50
apurvanandan[m]
I know how much useful it is, I am switching definitely once things work
01:53
apurvanandan[m]
https://pastebin.com/hMYQdaS2
01:54
apurvanandan[m]
https://pastebin.com/q2GiTUeC
01:54
apurvanandan[m]
Now they are formatted well
02:04
Bertl
why is the FIFO running at 300MHz?
02:06
Bertl
cdc_fifo_inst
02:09
Bertl
and regarding 'how much useful it is, I am switching definitely once things work' this is definitely the wrong approach, because you are now wasting (your and my) time with 'GUI problems' which would be better spent on 'actual problems'
02:15
aSobhy
finished it \o/
02:16
Bertl
top.tcl?
02:19
aSobhy
yes but I'll push the latest update now
02:19
aSobhy
just 1 min
02:26
aSobhy
https://github.com/aabdosobhy/Bi-Direction-packet-protocol/tree/master/Training/ZYNQ
02:27
aSobhy
Its the same link
02:27
Bertl
vivado -mode tcl -source top.tcl ?
02:28
aSobhy
yes and you didn't need to do "cd build.vivado "
02:28
Bertl
yes, I saw that
02:29
aSobhy
okay
02:30
aSobhy
Its giving an error didn't appear before sorry sorry
02:31
Bertl
yeah, DRC INBB-3
02:32
aSobhy
I didn't do that before
02:33
aSobhy
It*
02:38
Bertl
further hints are in the critical warnings ...
02:38
Bertl
[Project 1-486] Could not resolve non-primitive black box cell 'sh_2b_rg' instantiated as 'train_inst/word_8b_Reg'
02:44
aSobhy
yeah I found them
02:45
aSobhy
and running again to check it solved or not
02:45
aSobhy
I'm very sorry
02:48
aSobhy
Bertl how many cores I can specify to be run on any machine
02:49
aSobhy
don't tell me one please xD its very slow
02:49
Bertl
doesn't matter much, Vivado is terribly bad on using multiple cores
02:49
Bertl
but you can specify up to 10 for me
02:51
aSobhy
okay that's grade I'll make them 4
02:51
Bertl
if you do not specify it, it should use all available cores
02:52
Bertl
if you specify it as '4' it will be limited to that
02:54
aSobhy
no when I reduce it to 1 it didn't add "-jobs 4" -to the max- I think
02:57
aSobhy
the error is fixed
03:01
Bertl
mkdir: cannot create directory ‘build.vivado’: File exists :)
03:01
aSobhy
ah I delete that file before runing
03:02
aSobhy
folder*
03:02
Bertl
also you want to make sure that the case is correct
03:03
Bertl
Shift_2b_reg.vhd' does not exist
03:03
Bertl
shift_2b_reg.vhd does
03:04
aSobhy
no its exist !
03:04
Bertl
note the lower case 's' versus the upper case 'S'
03:04
Bertl
on most filesystems those are different
03:06
aSobhy
yeah I missed that
03:06
aSobhy
I changed it :)
03:11
Bertl
so for the set_property
03:11
aSobhy
yes
03:11
Bertl
set_property PACKAGE_PIN T9 [get_ports "lvds_p"]
03:11
Bertl
should work
03:13
Bertl
actually
03:13
Bertl
set_property PACKAGE_PIN T9 [get_ports {lvds_p}]
03:13
Bertl
is better
03:13
aSobhy
I tried that first It didn't change
03:14
aSobhy
set_property PACKAGE_PIN T9 [get_ports "lvds_p"] is running now
03:15
Bertl
it works on the tcl console (with your project) so it should be fine
03:20
aSobhy
maybe I missed something but finally \o/
03:22
Bertl
congratulations on your first Zynq bitstream! :)
03:22
Bertl
(I wish I would have said that six weeks ago :/)
03:23
aSobhy
I can't celebrate now Its still running
03:26
aSobhy
I need a time machine now :)
03:26
aSobhy
thanks Bertl for your help :) :)
03:26
Bertl
np
03:27
Bertl
you might also consider switching from the project based workflow to the non-project based as it is a lot faster
03:40
aSobhy
but It gives a warning that their is no T9 pin name
03:40
aSobhy
what part we are using
03:40
aSobhy
I used Zynq-7000
03:41
aSobhy
xc7z020clg484-1
03:41
aSobhy
is that right?
03:41
Bertl
xc7z020clg400-1
03:42
Bertl
it is defined in the BOARD_PART
03:42
Bertl
em.avnet.com:microzed_7020:part0:1.0
03:42
aSobhy
ok
03:42
Bertl
(or 1.1 if you have a more recent vivado)
03:43
aSobhy
I'll copy it from the vivado.tcl file its the same
03:50
aSobhy
the only part I have from em.avnet.com is xc7z020clg484-1
03:52
Bertl
did you install the MicroZed Board definition files?
03:52
Bertl
http://zedboard.org/support/documentation/1519
03:52
aSobhy
actually I didn't remember
03:53
aSobhy
OK I'll see that link
05:05
Bertl
off to bed now ... have a good one!
05:05
Bertl
changed nick to: Bertl_zZ
05:09
aSobhy
Good night :)
05:13
BAndiT1983|away
changed nick to: BAndiT1983
09:03
Y_|G
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10:09
illwieckz__
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illwieckz_
left the channel
11:21
BAndiT1983
changed nick to: BAndiT1983|away
12:07
Bertl_zZ
changed nick to: Bertl
12:07
Bertl
morning folks!
12:08
apurvanandan[m]
Good morning Bertl
12:08
apurvanandan[m]
I was waiting for you
12:09
apurvanandan[m]
Sorry, I fell asleep today in morning
12:09
Bertl
what's up?
12:10
apurvanandan[m]
Is there a way we can skip a clock cycle every 5 cycles, like 10101010001010101000...
12:11
apurvanandan[m]
Without using falling_edge trigger
12:11
Bertl
a gated clock can do that
12:12
apurvanandan[m]
Basically I want to leave one repeated 10b data due to 4:5 gearing in DDRX4 without using falling edges
12:12
Bertl
not sure what you mean
12:13
apurvanandan[m]
You told that falling edge creates timing issues, so I am eliminating those
12:14
apurvanandan[m]
So when you group 5 8bits words into 4 10bits, one clock cycle is only used for sampling new data right?
12:14
apurvanandan[m]
Sampling the first 8 bits every cycle
12:14
Bertl
falling edges do not create more timing issues than rising edges but mixing them or alternating them will
12:15
apurvanandan[m]
Yeah, all my design has rising edge except one process that eliminates a clock cycle
12:15
Bertl
why would you modify the clock?
12:16
apurvanandan[m]
So in DDR x4 when first 8 bits are received, you don't have a 10b word, so you wait for next clock cyles and then send 10b from 16b received
12:17
apurvanandan[m]
So on reception of first 8b , not data output clock is given
12:18
apurvanandan[m]
You told me this remember?
12:18
Bertl
yes, but I didn't tell you to mess with the clock
12:18
Bertl
it's just that one of the five clock cycles does not produce new data
12:19
Bertl
what do you do with the data?
12:19
Bertl
i.e. what is the next step after the 5x8:4x10 gearing?
12:20
apurvanandan[m]
Send it to decoder with same clock and then to fifo with same clock
12:20
Bertl
so where is the problem?
12:21
Bertl
you do not need to use every decoded value
12:21
apurvanandan[m]
If I use the same clock, it will take it as new data ?
12:21
Bertl
there are 4 clock cycles where the 10bit values are correct and one where you need to wait
12:22
apurvanandan[m]
Okay, my approach was wrong here
12:22
Bertl
the decoder has to run at the speed of the clock anyway, so it will produce 5 'decoded' values
12:22
Bertl
one of them will be incorrect, because it is from the wait cycle
12:23
Bertl
at the FIFO, you only add the 4 correct ones
12:23
Bertl
and simply ignore the fifth cycle
12:23
Bertl
this only requires a simple counter which you already have to adjust the mux to combine the 8bit words
12:25
apurvanandan[m]
Okay, so I can do that by making write enable '0' of the fifo at that cycle?
12:25
Bertl
precisely
12:25
apurvanandan[m]
Ok nice, my problem solved :)
12:26
Bertl
you can also avoid that the decoder gets a wrong word
12:26
apurvanandan[m]
By introducing an enable signal in decoder?
12:27
Bertl
yep
12:27
Bertl
if the decoder has a state
12:27
Bertl
i.e. if it tracks what was decoded, then you want to do that
12:28
Bertl
if it doesn't care and just decodes the word, then you can either send the old (valid) word or a bad word depending how your logic around error and comma detection works
12:28
apurvanandan[m]
Decoder samples data at both rising and falling edge
12:29
Bertl
that sounds wrong
12:29
apurvanandan[m]
It is the one taken from FreeCores.org
12:30
apurvanandan[m]
Sorry opencores.org
12:30
Bertl
what is the purpose of 'sampling' at both edges when you only provide data at rising edge?
12:32
apurvanandan[m]
The encoder uses both edges but the decoder uses only negedge
12:32
apurvanandan[m]
https://github.com/freecores/8b10b_encdec/blob/master/8b10_dec.vhd
12:34
Bertl
odd choice ... will certainly cause some timing issues
12:34
apurvanandan[m]
:/
12:34
apurvanandan[m]
Will try to correct that also
12:36
apurvanandan[m]
Also one more question
12:37
apurvanandan[m]
DLLDEL: deser_inst/ddrx1_inst/Inst4_DLLDELC CLKI has no preference. A preference is required that provides the period of the clock to calculate the 90 degree delay.
12:38
apurvanandan[m]
I get this warning when I don't write FREQUENCY PORT "CLK_LANE" 300.000000 MHz ; in constraints file
12:38
apurvanandan[m]
But when I do I get lot of negative slack
12:39
Bertl
this is like saying: it's all fine when I do not do timing checks, but it suddenly gives timing errors when I check :)
12:39
apurvanandan[m]
oh, sorry :/
12:39
Bertl
if you do not specify the clock/phase information to the tools, they will not report problems
12:40
apurvanandan[m]
:O
12:40
Bertl
you need to have a number of timing constraints, not just for clocks, also for input/output delays for static timing analysis to make any sense
12:40
apurvanandan[m]
So is mentioning FREQUENCY PORT "CLK_LANE" 300.000000 MHz ; correct?
12:41
Bertl
if your CLK_LANE has 300MHz then yes
12:42
apurvanandan[m]
Where can I learn how to write constraints?
12:43
Bertl
http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/RZ/Timing_Closure_Document.pdf?document_id=45588
12:44
apurvanandan[m]
Thanks Bertl, that was a great help
12:44
Bertl
you're welcome!
13:25
Bertl
off for now .. bbl
13:25
Bertl
changed nick to: Bertl_oO
13:26
danieel
apurvanandan[m]: maybe you are looking for a "data valid" signal, which will take shape of 01111 over the time, that creates 4 used states in 5 periods of higher freq clock
13:27
danieel
having just 8 bit in the 10bit bus is the 0, and after that, you have 4 periods of full 10bits (and extra register prepares the remainder to be used with the newly coming 8bits)
13:43
apurvanandan[m]
Exactly danieel , thanks
14:59
Fares
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Umori
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Umori
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15:57
illwieckz__
changed nick to: illwieckz
16:14
apurvanandan[m]
Bertl, DDR x4 gearing also worked
16:14
apurvanandan[m]
Now I am able to receive counter correctly
16:15
apurvanandan[m]
There could be two reasons it wasn't working, one can be using gated clock other can be using 40 bits reg and read and writing at same time
16:16
apurvanandan[m]
for 4 to 5 gearing
16:17
apurvanandan[m]
I am now just using a 10 bit reg and rearranging the 8 bits on the spot to form the 10 bit word
16:17
apurvanandan[m]
Now I am going to overclock and lets see what happens
16:20
apurvanandan[m]
Also both word alignment methods ie the internal one in IDDRX4B and one made by me both are working :)
16:26
BAndiT1983|away
changed nick to: BAndiT1983
16:36
Bertl_oO
sounds good
17:38
BAndiT1983
changed nick to: BAndiT1983|away
17:39
BAndiT1983|away
changed nick to: BAndiT1983
18:41
aSobhy
Bertl how do I reset the ZYNQ?
18:42
aSobhy
and for the reset I chosed the signal called "pB22B_W" that conneted to the PIC16
18:43
aSobhy
Is that fine ?
18:47
aSobhy
**and for the RFW reset**
19:07
apurvanandan[m]
Bertl, The DDRX4 is also working only till 300 MHz, at 375MHz there are lot of bit errors
19:07
apurvanandan[m]
Unmet timing constraints should be the issue right?
19:12
davidak
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BAndiT1983
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19:44
davidak
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19:57
BAndiT1983|away
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20:03
Bertl_oO
aSobhy: you probably do not want to 'reset' the Zynq
20:03
Bertl_oO
because that will reboot the Beta
20:04
Bertl_oO
apurvanandan[m]: very likely, you need to make sure your design passes all timing checks with proper constraints
20:10
aSobhy
ok I mean to reset my modules
20:11
Bertl_oO
you can do that in many ways, for example via one of the EIOs
20:13
aSobhy
like what?
20:13
Bertl_oO
you mean, what other ways except for an EIO?
20:14
Bertl_oO
AXI Bus (register mapping), JTAG Bus, via the fclk reset interface ...
20:16
aSobhy
no I mean the EIOs, how can I do that
20:17
Bertl_oO
you simply use them, they are a direct connection between fabric and arm cores
20:17
Bertl_oO
Linux supports them as GPIO interface
20:18
Bertl_oO
(but you can also access the registers directly)
20:18
Bertl_oO
EMIO* on the fabric side (part of the PS)
20:24
apurvanandan[m]
Bertl, Most of the timing errors are in the soft ip RX_SYNC
20:24
apurvanandan[m]
I mean all the errors
20:25
apurvanandan[m]
As it was mentioned that it can be given any slow clock for reset sync, I divided the fast edge clock and gave it
20:26
Bertl_oO
well, fix it
20:27
aSobhy
Is that what we are talking about ?
20:27
aSobhy
MIO
20:27
aSobhy
Eight PS MIOs (0, 9-15) are shared between the Pmod connector on-board the MicroZed and
20:27
aSobhy
the JX2 MicroHeader. When plugged into a Carrier, it is intended that the PS MIO Pmod on the
20:27
aSobhy
MicroZed would not be used.
20:28
Bertl_oO
the MIOs are GPIOs too, but they are only connected to the PS side and are used for PS peripherials
20:28
Bertl_oO
what you want to use are the EMIOs which are connected to the fabric
20:29
Bertl_oO
they do not have a physical connection outside the ZYNQ
20:31
apurvanandan[m]
Bertl, all timing errors solved
20:31
Bertl_oO
good, what was the issue?
20:31
Bertl_oO
(or the solution :)
20:31
apurvanandan[m]
I used FT601 100MHz clock for reset syncronisation of DDR x4
20:32
Bertl_oO
that's the solution?
20:32
apurvanandan[m]
Earlier I had used the DDR input clock made it slow by counter
20:32
apurvanandan[m]
Now I am using FT601 clock
20:33
Bertl_oO
I'm pretty sure you just 'disabled' the timing checks
20:33
apurvanandan[m]
Yes that is the solution
20:33
Bertl_oO
double check that cross clock domain timing is checked
20:34
Bertl_oO
because you probably just made things worse :)
20:34
apurvanandan[m]
Do you want to have a look over timing report?
20:34
Bertl_oO
yes, especially the part related to the reset
20:34
apurvanandan[m]
I also know this at the back of mind :/
20:35
apurvanandan[m]
ahh, It isn't showing that rx part now
20:50
illwieckz_
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20:53
apurvanandan[m]
Yes, Bertl I instantiated internal oscillator and now it is showing reset sync signals and they have timing closure correct, no negative slacks
20:53
apurvanandan[m]
Does it means the problem is fixed?
20:53
illwieckz
left the channel
20:54
aSobhy
sorry Bertl I'm searching to understand more
20:57
Bertl_oO
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/cmv_hdmi3/top.vhd
20:57
apurvanandan[m]
https://pastebin.com/tcqeWUye
20:57
Bertl_oO
search for emio there, you'll find the ps7 connections
20:58
aSobhy
OK that's great :)
20:59
apurvanandan[m]
https://pastebin.com/Lb9qfQ93
20:59
apurvanandan[m]
Here are the timing report for rx_sync reset sync module
21:00
Bertl_oO
Constraints cover 3152 paths, 7 nets, and 2140 connections (96.22% coverage)
21:01
Bertl_oO
what about the missing 3.88% ?
21:02
apurvanandan[m]
:o
21:02
Bertl_oO
(roughly about 120 pathes seems to have no constraints)
21:03
Bertl_oO
might be worth checking what those are
21:05
apurvanandan[m]
Trying that now, never did anything like this before :)
21:07
apurvanandan[m]
Ok found, It is a normal signal whose rising edge syncs the prngs and it happens only once
21:08
apurvanandan[m]
So it is routed using generic clock resource and can suffer from delays
21:08
Bertl_oO
okay, you might want to add an input constraint for that
21:09
Bertl_oO
or put it through a synchronizer
21:10
apurvanandan[m]
Okay
21:10
Bertl_oO
so just to recap, you now have DDR x1 and x4 running on virtex-5 to machxo2
21:11
apurvanandan[m]
yupp
21:11
Bertl_oO
and you get similar issues at about the same clock rate
21:11
apurvanandan[m]
Both at 300 MHz
21:11
apurvanandan[m]
not working at 375 or 400 MHz
21:11
Bertl_oO
and what is the datarate?
21:11
apurvanandan[m]
Yes similar issues
21:11
Bertl_oO
because 300 Mhz x1 means 600Mbit
21:12
Bertl_oO
but 300MHz x4 would be way above that :)
21:12
apurvanandan[m]
Yes 8/10 of that
21:12
apurvanandan[m]
means 480 Mbit
21:12
Bertl_oO
so the slow clock on x4 is actually 75MHz
21:13
apurvanandan[m]
Yes
21:13
Bertl_oO
okay
21:13
apurvanandan[m]
But in x4 the bandwitdh is 600 MBits only
21:13
Bertl_oO
so let's assume this is a problem of the connection
21:13
Bertl_oO
and let's try the same on the Beta
21:14
apurvanandan[m]
Nice idea
21:14
apurvanandan[m]
Is the usb module plugged there?
21:14
Bertl_oO
nobody has been at the hub, but as I said, I have one here
21:14
apurvanandan[m]
I will need to install D3XX on ZBox
21:15
Bertl_oO
another option would be to use the Main Board MachXO2
21:15
Bertl_oO
which is probably simpler to monitor (via the PIC)
21:15
apurvanandan[m]
I don't have much idea how PIC works
21:16
Bertl_oO
doesn't matter much, you can program the MachXO2 via the PIC
21:16
aSobhy
I want attend that process
21:16
apurvanandan[m]
XD
21:16
Bertl_oO
and you have two LVDS pairs on the RFE
21:16
Bertl_oO
so you can use one for clock and one for data for a test
21:17
Bertl_oO
aSobhy: yeah, you should have done this in the first two weeks ...
21:17
apurvanandan[m]
But how will I get FT601 data?
21:17
Bertl_oO
not at all
21:18
Bertl_oO
the simplest way to get the counter values (and that is basically all you want to know for BER) is via JTAG
21:18
apurvanandan[m]
I would prefer the USB module Bertl please
21:19
apurvanandan[m]
I can work with multiple channels till then
21:19
Bertl_oO
aSobhy: so it seems you still have some time to get BER running :)
21:21
apurvanandan[m]
Bertl, why is baudrate 600MBit in both cases?
21:21
Bertl_oO
hmm?
21:21
apurvanandan[m]
Is x1 and x4 just about bit grouping for output word
21:22
apurvanandan[m]
Both are just DDR
21:22
aSobhy
:/
21:26
apurvanandan[m]
One genuine question, DDRX4 offers data width parameters also, ie I can have 5 LVDS lanes make it [5:0] data bus input. Other thing that I can do is instantiate 5 DDR x4 modules and join 5 FIFOs and then to FTDI
21:27
apurvanandan[m]
Which method seems better to you?
21:28
Bertl_oO
the difference between x1, x2 and x4 DDR (and also the 7:1 gearing) is that you get a lower clock rate with a wider bus
21:29
Bertl_oO
i.e. x1 gives you halve of the DDR rate which is equal to your high speed clock
21:29
Bertl_oO
x2 gives you a quarter (i.e. half the high speed clock)
21:29
Bertl_oO
and x4 gives you one eight (i.e. a quarter of the high speed clock)
21:33
apurvanandan[m]
Thanks, the small doubt due to naming got cleared
21:34
apurvanandan[m]
And what should I prefer one single DDRx4 for all five lanes or five different DDRx4 instantiated one each for each lane
21:35
illwieckz_
changed nick to: illwieckz
21:35
Bertl_oO
ideally you get rid of the IPexpress wrappers and use the ODDRX4
21:36
Bertl_oO
s/ODDR/IDDR/
21:36
apurvanandan[m]
There isn't any part of IPexpress left, its just module instantiation
21:37
apurvanandan[m]
But IDDR can take data as busses
21:37
Bertl_oO
so how would you do five lanes with one IDDR4?
21:38
apurvanandan[m]
Ok, sorry my bad
21:38
apurvanandan[m]
I got my answer
21:39
Bertl_oO
the 'bus' feature is something IPexpress adds to the wrapper
21:39
Bertl_oO
anyway, you might want to check what lanes can support x4
21:39
apurvanandan[m]
Yeah I realized that just now
21:39
Bertl_oO
because IIRC, it's not available on all pins
21:40
Bertl_oO
so you might need to use x2 or x1 after all and do the gearing yourself
21:40
apurvanandan[m]
The ones you joint to LVDS must be having that no?
21:40
apurvanandan[m]
*joined
21:52
apurvanandan[m]
Okay all the lanes have it mp as per schematics
21:55
Bertl_oO
the IDDRX4B primitive can only be used on A/B pairs of the I/O cells at the bottom side of the device
21:55
apurvanandan[m]
Yupp
21:55
Bertl_oO
now I knew that it has to be the bottom side, so that is covered
21:55
apurvanandan[m]
Yes
21:57
Fares
Hi, as update, I pushed a draft report please check it and advise me what other thing I need to add to the report. And also I run the random test on the FPGA for 4 days and tested more that 23k RAW12 frames with all validated successfully.
21:57
Bertl_oO
but LVDS_3 is on PB11C/D
21:57
Bertl_oO
Fares: url?
21:58
Bertl_oO
apurvanandan[m]: and LVDS_0 is on PB18C/D
21:59
Bertl_oO
we might be able to move LVDS_3 to PB11A/B in a future revision, but that is not an option for LVDS_0
21:59
apurvanandan[m]
So should I go back to DDR x1?
22:00
Bertl_oO
also I didn't check the pinout differences between MachXO2 1200 and 2000
22:00
Bertl_oO
it might be a non-issue on the 2000
22:02
Bertl_oO
aSobhy: what are you currently working on, maybe I can help you a little
22:03
aSobhy
I switched to RFE to overcome the rest problem
22:03
Bertl_oO
s/rest/reset/?
22:04
aSobhy
I will use jx1_SE_0 to be the reset for both (ZYNQ, MachXO2)
22:05
aSobhy
and one lvds is clock and the other is the data
22:05
aSobhy
is that right ?
22:05
aSobhy
reset problem*
22:05
Bertl_oO
should work, but it would probably be better the other way round in the future
22:06
BAndiT1983
changed nick to: BAndiT1983|away
22:06
Bertl_oO
i.e. use the 'clock pin' for a common clock
22:07
Bertl_oO
also regarding reset, a simple but effective way to generate a reset is to have a special line state for this
22:07
Fares
sorry for the delay, it is currently on github https://github.com/FaresMehanna/JPEG-1992-lossless-encoder-core/blob/master/Report.pdf
22:07
Bertl_oO
aSobhy: e.g. if you are sending PRNG data, you have a forbidden state (all '0' or all '1')
22:08
Bertl_oO
so assuming you are sending 8bit data, you will never enounter 16 zeros or 16 ones in a row (depending on the LFSR type)
22:10
Bertl_oO
(let's assume zeros for now) which means that you just need to count 16 clock cycles while the signal is '0' and then you can assume a reset
22:10
Bertl_oO
more importantly, on the first non zero, you can resume operation
22:11
Bertl_oO
but as I said, it's fine to use the shared clock for a test
22:13
aSobhy
that's another way to reset the receiver
22:13
aSobhy
but in my case now the ZYNQ is the sender
22:14
Bertl_oO
does that make any difference for the reset?
22:17
Bertl_oO
Fares: what's the status of the integration with the Beta?
22:17
aSobhy
nope
22:20
Fares
well, I have not work on integrating it into beta, but the core has two axi stream interfaces which will make it quite easy to integrate
22:20
Fares
when I looked into how hdmi is working, it was reader -> fifo -> hdmi_logic
22:21
Fares
the LJ92 will be quite similar, but should I integrate it with the current beta VHDL files?
22:22
Bertl_oO
it would be great to try an integration with the existing beta firmware, for example just use one HDMI output as data sink for the encoded image
22:22
apurvanandan[m]
Bertl, do you have schematics of machXO2 2000HC
22:23
Bertl_oO
once we get the USB 3 plugin working, it should then be easy to switch from HDMI to USB and have the full LJ92 functionality
22:23
Bertl_oO
apurvanandan[m]: you probably mean the pinout :)
22:23
apurvanandan[m]
Yupp sorry
22:24
Bertl_oO
pinouts can be downloaded from lattice
22:24
Bertl_oO
https://www.latticesemi.com/view_document?document_id=43047
22:26
Bertl_oO
ah yes, on 2000HC, all those are A/B
22:26
apurvanandan[m]
yes I saw :D
22:26
Bertl_oO
so x4 is no problem there for any of the LVDS pairs
22:26
apurvanandan[m]
happy
22:27
Fares
Ok I will do that, replacing hdmi logic with lj92 core logic. I will be using the beta's gateware that is currently hosted in the github, correct?
22:27
Bertl_oO
apurvanandan[m]: now the other question is the clock input
22:27
apurvanandan[m]
I didn't get
22:27
Bertl_oO
Fares: yes, that should be the most recent version
22:27
apurvanandan[m]
Clock is LVDS too?
22:28
Bertl_oO
Fares: but please double check that it builds correctly before starting the integration :)
22:28
Bertl_oO
apurvanandan[m]: well, you want to use one LVDS pair as clock
22:29
Bertl_oO
you definitely want to use a clock capable input for that :)
22:29
apurvanandan[m]
Currently I am on clock capable pin mp
22:29
Bertl_oO
hmm?
22:30
apurvanandan[m]
ie PB11A/B
22:30
Fares
can you please explain what exactly the component that "it builds correctly"?
22:30
apurvanandan[m]
pin 34,35
22:30
apurvanandan[m]
They are clock capable i think
22:30
Bertl_oO
ah, yes, the are PCLK*2_0
22:30
apurvanandan[m]
:)
22:31
Bertl_oO
and that is actually the only pair we have there
22:31
apurvanandan[m]
I remember I sorted this thing out initailly
22:32
Bertl_oO
good, then that's sorted
22:32
apurvanandan[m]
everything is sorted, now lets do it :)
22:33
Bertl_oO
go ahead, 3.2Gbit/s today! :)
22:33
Bertl_oO
I'll test it in the evening :)
22:33
apurvanandan[m]
Perfect
22:40
Fares
?
23:14
Bertl_oO
what I meant is, just rebuild the entire thing to see that it 'still works'
23:14
apurvanandan[m]
By the way, DDR x1 is performing better than x4 in terms of BER
23:15
apurvanandan[m]
DDR x4 has BER of 10^-8
23:15
Bertl_oO
Fares: if you use a different Vivado version or if you are missing board definition files, etc, it might cause problems with the integration (better to sort them out beforehand)
23:16
Bertl_oO
apurvanandan[m]: might be related to the actual timing (placement/routing) or to the training
23:16
apurvanandan[m]
Hmm, I see
23:17
Bertl_oO
so it would be advised to test a few different implementations (with different optimizations, etc)
23:17
apurvanandan[m]
Okay
23:17
apurvanandan[m]
I am cleaning up the code
23:37
Fares
left the channel
23:53
Fares
joined the channel
23:53
Fares
Ok great, I will do, thank you for your time.
23:53
Bertl_oO
my pleasure!