#apertus IRC Channel Logs

Bertl where you set the Directory in "vivado.tcl" ?

(cd build.vivado && vivado -mode tcl -source ../vivado.tcl)

I searched It sets the directory from the where it typed that command but on my side don't

I asked to see If their is a way to set the directory by command

try setting 'DIRECTORY'

i.e. set_property DIRECTORY [current_project] ...

negative slack usually arises from either excessive path delay or from clock skew

pastebin?

well, specifically the timing path for one (or more) of the problematic ones (with negative slack)

https://pastebin.com/u8Kk8ixH

the paste is rather unreadable btw :)

no It didn't accept it

https://github.com/apurvanandan1997/BER_mesurement_x1

so how do I build it?

Do you have Diamond 3?

Open the ber_measure.ldf in proj folder from open project in Diamond

I found a way :)

aSobhy: excellent! let's hear!

there is no 'Generate bitsream' under 'Process'

It is in process tab

Yes the bitsream file under export files

After that you want to go to Tools menu above in menu bar, then timing analysis view option

Yes, once it finish we can see timing analysis from the tools menu

few seconds

http://vserver.13thfloor.at/Stuff/GSoC2019/apurva_diamond2.jpg

(no output, nothing, just spinning)

Rightclick and stop

:)

diamond segfaults

yep, sorry, Tools

Segmentation fault (core dumped)

how about you switch the project to commandline build

I know how much useful it is, I am switching definitely once things work

https://pastebin.com/q2GiTUeC

why is the FIFO running at 300MHz?

and regarding 'how much useful it is, I am switching definitely once things work' this is definitely the wrong approach, because you are now wasting (your and my) time with 'GUI problems' which would be better spent on 'actual problems'

top.tcl?

just 1 min

Its the same link

yes and you didn't need to do "cd build.vivado "

okay

yeah, DRC INBB-3

It*

[Project 1-486] Could not resolve non-primitive black box cell 'sh_2b_rg' instantiated as 'train_inst/word_8b_Reg'

and running again to check it solved or not

Bertl how many cores I can specify to be run on any machine

doesn't matter much, Vivado is terribly bad on using multiple cores

okay that's grade I'll make them 4

if you specify it as '4' it will be limited to that

the error is fixed

ah I delete that file before runing

also you want to make sure that the case is correct

shift_2b_reg.vhd does

note the lower case 's' versus the upper case 'S'

yeah I missed that

so for the set_property

set_property PACKAGE_PIN T9 [get_ports "lvds_p"]

actually

is better

set_property PACKAGE_PIN T9 [get_ports "lvds_p"] is running now

maybe I missed something but finally \o/

(I wish I would have said that six weeks ago :/)

I need a time machine now :)

np

but It gives a warning that their is no T9 pin name

I used Zynq-7000

is that right?

it is defined in the BOARD_PART

ok

I'll copy it from the vivado.tcl file its the same

did you install the MicroZed Board definition files?

actually I didn't remember

off to bed now ... have a good one!

Good night :)

Good morning Bertl

Sorry, I fell asleep today in morning

Is there a way we can skip a clock cycle every 5 cycles, like 10101010001010101000...

a gated clock can do that

not sure what you mean

So when you group 5 8bits words into 4 10bits, one clock cycle is only used for sampling new data right?

falling edges do not create more timing issues than rising edges but mixing them or alternating them will

why would you modify the clock?

So on reception of first 8b , not data output clock is given

yes, but I didn't tell you to mess with the clock

what do you do with the data?

Send it to decoder with same clock and then to fifo with same clock

you do not need to use every decoded value

there are 4 clock cycles where the 10bit values are correct and one where you need to wait

the decoder has to run at the speed of the clock anyway, so it will produce 5 'decoded' values

at the FIFO, you only add the 4 correct ones

this only requires a simple counter which you already have to adjust the mux to combine the 8bit words

precisely

you can also avoid that the decoder gets a wrong word

yep

i.e. if it tracks what was decoded, then you want to do that

Decoder samples data at both rising and falling edge

It is the one taken from FreeCores.org

what is the purpose of 'sampling' at both edges when you only provide data at rising edge?

https://github.com/freecores/8b10b_encdec/blob/master/8b10_dec.vhd

:/

Also one more question

I get this warning when I don't write FREQUENCY PORT "CLK_LANE" 300.000000 MHz ; in constraints file

this is like saying: it's all fine when I do not do timing checks, but it suddenly gives timing errors when I check :)

if you do not specify the clock/phase information to the tools, they will not report problems

you need to have a number of timing constraints, not just for clocks, also for input/output delays for static timing analysis to make any sense

if your CLK_LANE has 300MHz then yes

http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/RZ/Timing_Closure_Document.pdf?document_id=45588

you're welcome!

having just 8 bit in the 10bit bus is the 0, and after that, you have 4 periods of full 10bits (and extra register prepares the remainder to be used with the newly coming 8bits)

Bertl, DDR x4 gearing also worked

There could be two reasons it wasn't working, one can be using gated clock other can be using 40 bits reg and read and writing at same time

I am now just using a 10 bit reg and rearranging the 8 bits on the spot to form the 10 bit word

Also both word alignment methods ie the internal one in IDDRX4B and one made by me both are working :)

sounds good

and for the reset I chosed the signal called "pB22B_W" that conneted to the PIC16

**and for the RFW reset**

Unmet timing constraints should be the issue right?

because that will reboot the Beta

ok I mean to reset my modules

like what?

AXI Bus (register mapping), JTAG Bus, via the fclk reset interface ...

you simply use them, they are a direct connection between fabric and arm cores

(but you can also access the registers directly)

Bertl, Most of the timing errors are in the soft ip RX_SYNC

As it was mentioned that it can be given any slow clock for reset sync, I divided the fast edge clock and gave it

Is that what we are talking about ?

Eight PS MIOs (0, 9-15) are shared between the Pmod connector on-board the MicroZed and

MicroZed would not be used.

what you want to use are the EMIOs which are connected to the fabric

Bertl, all timing errors solved

(or the solution :)

that's the solution?

Now I am using FT601 clock

Yes that is the solution

because you probably just made things worse :)

yes, especially the part related to the reset

ahh, It isn't showing that rx part now

Yes, Bertl I instantiated internal oscillator and now it is showing reset sync signals and they have timing closure correct, no negative slacks

http://vserver.13thfloor.at/Stuff/AXIOM/BETA/cmv_hdmi3/top.vhd

search for emio there, you'll find the ps7 connections

https://pastebin.com/Lb9qfQ93

Constraints cover 3152 paths, 7 nets, and 2140 connections (96.22% coverage)

:o

might be worth checking what those are

Ok found, It is a normal signal whose rising edge syncs the prngs and it happens only once

okay, you might want to add an input constraint for that

Okay

yupp

Both at 300 MHz

and what is the datarate?

because 300 Mhz x1 means 600Mbit

Yes 8/10 of that

so the slow clock on x4 is actually 75MHz

okay

so let's assume this is a problem of the connection

Nice idea

nobody has been at the hub, but as I said, I have one here

another option would be to use the Main Board MachXO2

I don't have much idea how PIC works

I want attend that process

and you have two LVDS pairs on the RFE

aSobhy: yeah, you should have done this in the first two weeks ...

not at all

I would prefer the USB module Bertl please

aSobhy: so it seems you still have some time to get BER running :)

hmm?

Both are just DDR

One genuine question, DDRX4 offers data width parameters also, ie I can have 5 LVDS lanes make it [5:0] data bus input. Other thing that I can do is instantiate 5 DDR x4 modules and join 5 FIFOs and then to FTDI

the difference between x1, x2 and x4 DDR (and also the 7:1 gearing) is that you get a lower clock rate with a wider bus

x2 gives you a quarter (i.e. half the high speed clock)

Thanks, the small doubt due to naming got cleared

s/ODDR/IDDR/

But IDDR can take data as busses

Ok, sorry my bad

the 'bus' feature is something IPexpress adds to the wrapper

Yeah I realized that just now

so you might need to use x2 or x1 after all and do the gearing yourself

*joined

the IDDRX4B primitive can only be used on A/B pairs of the I/O cells at the bottom side of the device

now I knew that it has to be the bottom side, so that is covered

Hi, as update, I pushed a draft report please check it and advise me what other thing I need to add to the report. And also I run the random test on the FPGA for 4 days and tested more that 23k RAW12 frames with all validated successfully.

Fares: url?

we might be able to move LVDS_3 to PB11A/B in a future revision, but that is not an option for LVDS_0

also I didn't check the pinout differences between MachXO2 1200 and 2000

aSobhy: what are you currently working on, maybe I can help you a little

s/rest/reset/?

and one lvds is clock and the other is the data

reset problem*

also regarding reset, a simple but effective way to generate a reset is to have a special line state for this

aSobhy: e.g. if you are sending PRNG data, you have a forbidden state (all '0' or all '1')

(let's assume zeros for now) which means that you just need to count 16 clock cycles while the signal is '0' and then you can assume a reset

but as I said, it's fine to use the shared clock for a test

but in my case now the ZYNQ is the sender

Fares: what's the status of the integration with the Beta?

well, I have not work on integrating it into beta, but the core has two axi stream interfaces which will make it quite easy to integrate

the LJ92 will be quite similar, but should I integrate it with the current beta VHDL files?

Bertl, do you have schematics of machXO2 2000HC

apurvanandan[m]: you probably mean the pinout :)

pinouts can be downloaded from lattice

ah yes, on 2000HC, all those are A/B

so x4 is no problem there for any of the LVDS pairs

Ok I will do that, replacing hdmi logic with lj92 core logic. I will be using the beta's gateware that is currently hosted in the github, correct?

I didn't get

Clock is LVDS too?

apurvanandan[m]: well, you want to use one LVDS pair as clock

Currently I am on clock capable pin mp

ie PB11A/B

pin 34,35

ah, yes, the are PCLK*2_0

and that is actually the only pair we have there

good, then that's sorted

go ahead, 3.2Gbit/s today! :)

Perfect

what I meant is, just rebuild the entire thing to see that it 'still works'

DDR x4 has BER of 10^-8

apurvanandan[m]: might be related to the actual timing (placement/routing) or to the training

so it would be advised to test a few different implementations (with different optimizations, etc)

I am cleaning up the code

my pleasure!