#apertus IRC Channel Logs

good morning

anybody interested in helping out with data collection?

Bertl: what data collection?

good night

yo

re.

hey, what kind of update do you have in mind?

After making me wait for a decision for 3 weeks, Cruse have bowed out of the prelim study

so i need to decide myself whether I go with zedboard, microzed or something else

SFE?

and microzed doesn't?

a possible alternative for me might be to use *something* with a Lattice LVDS bridge

whole point here is I am not sure yet. I don't have a sensor choice.

I remember

maybe I should just order *anything* t get off the ground. Whatever happens I will need to make a sensor interface, it looks like.

like tool setup, synthesis, debugging, testing, etc

ideally, I would use a platform that exists, but that doesn't seem to exist :(

?

for the right price, we can probably build another axiom alpha for you and have it shipped (without sensor) in a week or so :)

a few thousand euro I guess, it would have to make sense for us to spend time on that

but the point is, it's not that the platform doesn't exist, it is just to much money or efford for you to get it :)

we haven't decided yet, but the basic setup will be rather affordable

I get your point. If it were a camera it would be no problem. But as a development tool that has a limited lifetime it's different

I guess so, just make sure that you do not miss the crowdfunding, as it will be hard to get one in the beginning

and you probably want to benefit from the extra nice price as well

you measure the patches, in decent light, and then you write the code which creates the matrix.

well, we could swap a decent measurement instrument for a board :)

It works with Graeme Gill's Argyll

so I'm thinking of revisiting this stuff myself.

I can try to remember, but it's probably better to check periodically on the web site

I'm sure you won't be able to miss it there :)

how hard is it to get lvds signals on/off the microzed?

Soy seem to be using micro-lvds, with a 0.9V center point (I don't know the terminology)

the connectors feature 2x24LVDS pairs on two 100pin FCI connectors

can the center voltage be adjusted or is it fixed?

ah.

the common voltage is not a big problem on the xilinx fpgas, the swing could be, not sure how much the zynq requires

Ah. That is good news. I only need a few lines initially, can multiplex probably, because I'm doing stills.

I mean, the chip can be said to use only a few lines, I think.

and as I can wait for the image ...

bye