Current Server Time: 07:16 (Central Europe)

#apertus IRC Channel Logs

2021/01/03

Timezone: UTC


23:15
mumptai
left the channel
00:06
illwieckz
left the channel
00:06
Umori
left the channel
00:06
vup
left the channel
00:09
illwieckz
joined the channel
00:09
Umori
joined the channel
00:09
vup
joined the channel
00:32
aombk2
joined the channel
00:33
aombk
left the channel
01:06
comradekingu
left the channel
01:33
comradekingu
joined the channel
01:37
vup2
joined the channel
01:38
Umori_
joined the channel
01:39
kbeckmann1
joined the channel
01:43
danieel
left the channel
01:43
kbeckmann
left the channel
01:43
madonius
left the channel
01:43
illwieckz
left the channel
01:43
Umori
left the channel
01:43
vup
left the channel
01:44
illwieckz_
joined the channel
01:50
madonius
joined the channel
01:55
danieel
joined the channel
03:29
illwieckz_
changed nick to: illwieckz
04:45
eppisai
joined the channel
06:01
Bertl_oO
off to bed now ... have a good one everyone!
06:01
Bertl_oO
changed nick to: Bertl_zZ
07:00
eppisai
left the channel
07:00
eppisai
joined the channel
07:15
BAndiT1983|away
changed nick to: BAndiT1983
08:07
eppisai_
joined the channel
08:08
eppisai
left the channel
08:08
eppisai_
changed nick to: eppisai
08:32
LordVan
joined the channel
10:55
mumptai
joined the channel
11:52
RexOrCine
left the channel
13:39
RexOrCine
joined the channel
15:04
Bertl_zZ
changed nick to: Bertl
15:04
Bertl
morning folks!
15:04
se6ast1an
good day!
16:09
eppisai
left the channel
16:10
eppisai
joined the channel
16:19
eppisai
left the channel
16:28
eppisai
joined the channel
16:49
BAndiT1983
changed nick to: BAndiT1983|away
16:49
BAndiT1983|away
changed nick to: BAndiT1983
17:01
LordVan
left the channel
17:34
eppisai
left the channel
17:34
eppisai
joined the channel
18:06
korken89
joined the channel
18:06
korken89
anuejn: o/
18:07
anuejn
so I guess what you are seeing is the ft600 sending less than 2048 bytes in a buffer
18:08
anuejn
If I remember correctly the fix for me was to have a fifo in front of the ft600 and start a transaction only if I am certain that I can finish it without pulling valid low
18:09
anuejn
which is what our ft601 driver core does
18:09
se6ast1an
sounds reasonable
18:09
anuejn
but if you have a link to your gateware I can have another look
18:09
anuejn
(this is the continuation of a discussion in #nmigen)
18:10
korken89
I pushed it here: https://github.com/korken89/ovio_core_firmware/blob/master/gateware/apps/ft600_test.py
18:10
korken89
Ah, so that is why you had the signal to start a transaction
18:10
korken89
I just send right now if there is something in the FIFO, no matter how full it is
18:11
korken89
So the FT60x has limits on packets?
18:11
korken89
From the datasheet it only says it will use smaller frames if not sending full 1024 byte packets
18:11
korken89
But I can also have misunderstood something :)
18:12
anuejn
yup it can do that but our rust driver does not support that atm ;)
18:12
korken89
Aaahh
18:12
anuejn
also the time the ft60x seems to need seems to be independent of the packet length so it is beneficial for performance anyways to always do full packets
18:13
korken89
Makes sense
18:13
anuejn
(smaller packets would be implementable but most likely not with our current zero coppy aproach so it would give us a performance hit on the pc side too)
18:13
anuejn
so you need something like https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/ft601/ft601_stream_sink.py#L29
18:13
anuejn
the whole save_to_begin_new_transaction logic from that file
18:14
korken89
In my case I'll have varying length data coming out, some packets are images of ~300 kB and some are IMU data reports of 40 bytes
18:15
korken89
I'll give it a try to see how the ft60x-rs interacts :)
18:15
anuejn
do you have any realtime requirement for your data stream?
18:15
korken89
Indeed
18:15
anuejn
if so: you can still read a smaller buffer with ft60x rs if you know the size beforehand
18:15
korken89
It's for VIO which expects sub 20 ms latency
18:16
korken89
Hmm, I need to figure out my data packets
18:16
korken89
As I was sort of just planning to packet each data type and ship it
18:16
korken89
Not really care about the USB FIFO part
18:16
anuejn
20ms doesnt sound like padding all data packets would hurt ;)
18:16
korken89
Haha, you have a point there
18:17
korken89
You run with fixed length frames?
18:17
anuejn
hm... no
18:17
anuejn
our setup is a bit more funky
18:17
korken89
Oh? Sounds interesting!
18:18
anuejn
as the usb3 plugin module has its own fpga (a machxo2) we have to run some interface between that fpga and the main fpga
18:18
anuejn
currently in this interface there is no "ready" signal planed
18:19
korken89
Hmm, it just pumps the data?
18:19
korken89
And the machxo2 just needs to keep up?
18:19
anuejn
so basically if the pc side (or the usb bus or whatever) cant keep up receiving the data we loose data in random places
18:19
korken89
Ah I see
18:19
anuejn
so we need an automatically alignig protocol
18:19
korken89
I wonder if COBS is hard to implement in HW
18:19
anuejn
therfore we did that framing hack with a blanking area to which we syncronize
18:20
korken89
Might be to heavy to decode on the PC side though
18:20
anuejn
ah but I guess I missunterstood your question
18:20
anuejn
yup our frames are expected to have always the same length
18:20
korken89
Haha no problem
18:20
korken89
I mean
18:21
korken89
I could have fixed frame sizes
18:21
korken89
I see no problem there
18:21
korken89
I'm just wondering what happens then if the FT60x reader looses sync, does this happen?
18:21
korken89
So I get 0.2 of one frame and 0.8 of the next
18:21
anuejn
it just resyncs again ;)
18:21
anuejn
and it does happen
18:22
anuejn
probably the current desing will not stay for long
18:22
korken89
Wait, you loose data?
18:22
korken89
Is this due to the "ready"-less design?
18:22
korken89
I was hoping to use the FT600 as a lossless pipe
18:22
anuejn
we will need a better plan anyways once we have wavelet compression
18:22
korken89
I won't be close to the max rate of it as well, I'll only use like 30-50 MB/s
18:23
anuejn
I think this is part of the ready-less design
18:23
korken89
I need to look deeper into apertus, get a feel for the architecture you use
18:24
anuejn
when i send a counter that is generated in the machxo2 I dont get any data loss
18:24
korken89
At least an overview
18:24
korken89
I feel there is a lot to learn from you all there :D
18:24
korken89
Nice!
18:24
anuejn
so your hope for a lossless pipe is probably fulfilled :)
18:24
korken89
I have been using the FT232H a lot in FIFO mode, so I just wanted a faster one :)
18:24
anuejn
If you have questions just ask :)
18:25
korken89
As I'll be like at max of what the FT232H can deliver
18:25
anuejn
Ah I see that
18:25
korken89
But I guess, if I pump the raw video I'll need like 55 MB/s
18:25
korken89
(not really what my board is supposed to do though)
18:26
korken89
But I'm sure some want to use it as "just" a stereo camera as well
18:26
korken89
+ debugging purposes
18:26
anuejn
I would really like to have something faster than the ft601, because 4k24p 12bit is already pushing the ft601 pretty hard ;)
18:26
korken89
> f you have questions just ask :)
18:26
korken89
Thanks, I'll keep you to that ;)
18:26
korken89
Haha
18:26
korken89
Actually I sort of wanted to directly connect to PCIe
18:27
anuejn
Oh I didnt notice that the MT9V034 was just vga
18:27
korken89
Yeah, good ol' tech
18:27
anuejn
is there any specific reason you went for that sensor?
18:28
korken89
It's very classical in the machine vision community
18:28
korken89
Had quite good HDR as well
18:28
korken89
I'm not planning to stick with it though
18:28
anuejn
I was kind of thinking if the ovio could be used as a better webcam with background removal
18:29
anuejn
ah I see hdr sounds like a strong argument
18:29
korken89
I just have used that camera a lot, and the first time I tried Lattice FPGAs I wanted something I was used to :)
18:29
anuejn
I see
18:29
korken89
Global shutter, HDR, and very short shutter times as well
18:29
korken89
Even in darker settings
18:29
anuejn
also vga seems a lot more chill to process
18:29
korken89
Perfect for fast moving drones :)
18:29
korken89
Yeah
18:29
korken89
VGA is actually more than enough for VIO
18:30
anuejn
is the ovio intendet to go on a drone?
18:30
korken89
Yeah
18:30
korken89
That was my research area :)
18:30
anuejn
ah nice now things start to make more sense to me
18:31
korken89
Hehe
18:31
korken89
On page 5 here you can see the platform I still use: https://arxiv.org/pdf/1812.04755.pdf
18:32
korken89
Sorry, I sort of assumed you knew what I was up to
18:32
korken89
I want an visual intertial odometry accelerator board is the final aim :)
18:33
korken89
And to run as much of the VIO algorithms in the FPGA as I can
18:33
anuejn
huh that seems like a power hungry platform
18:33
anuejn
now I understand your process
18:34
anuejn
is your aim to eliminate the computer on that copter altogether?
18:34
korken89
Not really, the high level algorithms still need it
18:34
anuejn
okay
18:34
anuejn
sounds like a fun project
18:34
korken89
But right now about 70% of all CPU power on the drone only goes into image convolutions, feature extraction etc
18:34
korken89
Things that an FPGA is perfect for
18:35
korken89
I love this area :D
18:35
anuejn
is that a university project?
18:35
anuejn
ah i see
18:35
korken89
It was before
18:36
korken89
A few colleagues from the lab and I are running a company now, that has nothing to do with drones nor cameras anymore
18:36
korken89
But I find the area so interesting that I sort of can't stop :)
18:36
korken89
So now it's a hobby instead
18:36
anuejn
ah I see
18:36
anuejn
nice :)
18:36
anuejn
btw: did you read https://github.com/nmigen/nmigen/issues/213
18:37
anuejn
(and the rigel paper)
18:37
korken89
Oh that looks interesting
18:37
anuejn
huh linked the wrong issue
18:38
korken89
Haha, was still interesting :D
18:38
korken89
Sounds great for processing pipelines
18:38
anuejn
ah no it was the right one
18:38
anuejn
was just confused by the issue importer
18:39
korken89
Would be a nice feature
18:39
anuejn
the cores in https://github.com/apertus-open-source-cinema/nmigen-gateware/tree/master/src/lib/video implement something in that direction but are not nearly as cool as the rigel stuff
18:39
korken89
How we used to implement the pipelines were like small modules with know delay and data width
18:39
anuejn
(e.g. no static scheduling, ...)
18:40
korken89
I'm so amazed by the nMigen area
18:40
korken89
We did all with raw VHDL and Jinja templates, and it was a true pain
18:41
anuejn
sounds... fun? :p
18:41
anuejn
I only started to do bigger fpga stuff when nmigen came up
18:41
korken89
Now in a few days I have learned enough nMigen to get the FT600 running, which was horrible before, and its really amazing!
18:41
korken89
Yeah same here
18:41
anuejn
so I am probably lacking most of the basics
18:42
korken89
I have 0 formal education in FPGAs :)
18:42
anuejn
yup me too
18:42
korken89
Or, I had one digital electonics course
18:42
korken89
But it was a VHDL + simulation, not even mentioning FPGAs
18:43
anuejn
I have basically 0 formal education on nothnig (just finished school)
18:43
korken89
With tools like nMigen it gets actually quite enjoyable :)
18:43
anuejn
jup
18:43
korken89
Oh
18:43
anuejn
(actually all the in depth math stuff / complex stuff comes from vup2)
18:43
anuejn
;)
18:44
korken89
Hehe
18:44
korken89
You picked up FPGAs just for fun?
18:44
anuejn
mainly because we wanted to get our camera working
18:45
korken89
Oh, you started with cameras?
18:45
anuejn
so yes, for fun
18:45
anuejn
yup somehow I stumbled into the apertus project a couple of years ago and since then I am quite into cameras ;)
18:46
korken89
Cool!
18:47
korken89
Is there like an arhc overview of the camera in the apertus project?
18:48
anuejn
hm... not really?
18:48
anuejn
se6ast1an: do you know one
18:48
korken89
No problem, I'm surfing around the repos :)
18:49
anuejn
sounds like a good plan :)
18:49
korken89
Nice camera IC
18:49
anuejn
actually there is one more thing I want to point you to (for gateware development)
18:49
korken89
Doit!
18:49
korken89
I'm very new to nMigen so all tips are welcome :)
18:50
anuejn
(disclaimer: it is a big hack and very unholy but hacky)
18:50
anuejn
the SocPlatform infrastructure in our nmigen-gateware
18:51
anuejn
it allows you to mark signals as "i want to be able to read / change this value at runtime"
18:51
korken89
Oh
18:52
korken89
Like a register to access via the FT600?
18:52
anuejn
then it generates some glue-logic to be able to access that register via jtag (currently used for the machxo; probably works for the ecp5 with some changes) or via axi (for the zynq)
18:52
se6ast1an
arhc?
18:52
korken89
Ohh
18:53
korken89
se6ast1an: arch *
18:53
anuejn
then it generates a python library which exposes those registers as fake python variables
18:53
anuejn
it is a bit like a crude form of what litex does
18:55
se6ast1an
ah, no sorry, not that I am aware of
18:55
korken89
So you get register access via the FPGA's JTAG?
18:56
anuejn
you can even define methods on your driver in your gareware codebase (example: https://github.com/apertus-open-source-cinema/nmigen-gateware/blob/master/src/lib/io/plugin_module_streamer/rx.py#L63)
18:56
anuejn
korken89: yup
18:59
korken89
Very cool
18:59
korken89
I have no idea how all that works, but sounds very nice for developments
19:00
anuejn
I can walk you trough the process of getting that up and running if you are interested
19:01
korken89
I'd like to give it a try :) Not today though, soon bedtime, but I'll take you up on that offer!
19:02
anuejn
okay, cool :)
19:04
korken89
Thanks for the help today! Quite fun to get the FT600 talking :D
19:05
anuejn
good luck and keep me posted :)
19:07
korken89
Will do!
19:39
eppisai
left the channel
19:41
Bertl
off for now ... bbl
19:41
Bertl
changed nick to: Bertl_oO
21:08
se6ast1an
off to bed
21:08
se6ast1an
good night
21:51
BAndiT1983
changed nick to: BAndiT1983|away
21:56
korken89
left the channel
22:41
mumptai
left the channel