Current Server Time: 01:02 (Central Europe)

#apertus IRC Channel Logs

2015/10/02

Timezone: UTC


00:20
slikdigit
left the channel
00:27
fsteinel
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00:27
fsteinel_
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02:33
Bertl
off to bed now ... have a good one everyone!
02:33
Bertl
changed nick to: Bertl_zZ
03:22
intracube
changed nick to: intracube|away
05:47
Bertl_zZ
changed nick to: Bertl
05:47
Bertl
morning folks!
06:52
comradekingu
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07:02
ItsMeLenny
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08:24
se6astian|away
changed nick to: se6astian
08:36
se6astian
good day
09:07
ItsMeLenny
hello
09:07
Bertl
hey Lenny, how's going?
09:15
irieger_
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09:16
alexML_
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09:17
alexML
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09:17
irieger
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10:18
fsteinel_
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10:52
ItsMeLenny
hey Bertl not bad, bit of a delayed reply :P
10:52
ItsMeLenny
on my part that is
10:54
Bertl
no problem with IRC
11:25
ItsMeLenny
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13:41
comradekingu
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14:29
Bertl
off for a nap ... bbl
14:29
Bertl
changed nick to: Bertl_zZ
14:53
cbohnens
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15:08
se6astian
changed nick to: se6astian|away
15:52
se6astian|away
changed nick to: se6astian
16:10
intracube|away
changed nick to: intracube
18:40
slikdigit
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20:44
Bertl_zZ
changed nick to: Bertl
20:44
Bertl
back now ...
21:19
se6astian
time for bed
21:19
se6astian
good night
21:19
se6astian
changed nick to: se6astian|away
21:26
Bertl
nn
21:30
aombk
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21:32
aombk3
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22:31
irieger_
changed nick to: irieger
22:50
irieger
Hey Bertl, I'm trying to understand the image pipeline of the Axiom better. Is there something that goes more in depth? Or where is the image processing code in the Github?
22:51
irieger
Is everything after the sensor happening on the FPGA part?
23:08
Bertl
https://wiki.apertus.org/index.php?title=Axiom_Alpha_Software
23:08
Bertl
there is a flow chart for the image pipeline
23:08
Bertl
the parts labeled "Fabric" are done in the FPGA
23:09
Bertl
for the Beta, the HDMI encoder is also part of the FPGA
23:10
Bertl
the code is on github (https://github.com/apertus-open-source-cinema/alpha-software)