Current Server Time: 02:39 (Central Europe)

#apertus IRC Channel Logs

2015/10/02

Timezone: UTC

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01:20
slikdigit
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01:27
fsteinel
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01:27
fsteinel_
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03:33
Bertl
off to bed now ... have a good one everyone!
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03:33
Bertl
changed nick to: Bertl_zZ
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04:22
intracube
changed nick to: intracube|away
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06:47
Bertl_zZ
changed nick to: Bertl
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06:47
Bertl
morning folks!
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07:52
comradekingu
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08:02
ItsMeLenny
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09:24
se6astian|away
changed nick to: se6astian
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09:36
se6astian
good day
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10:07
ItsMeLenny
hello
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10:07
Bertl
hey Lenny, how's going?
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10:15
irieger_
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alexML_
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alexML
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10:17
irieger
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11:18
fsteinel_
changed nick to: fsteinel
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11:52
ItsMeLenny
hey Bertl not bad, bit of a delayed reply :P
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11:52
ItsMeLenny
on my part that is
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11:54
Bertl
no problem with IRC
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12:25
ItsMeLenny
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14:41
comradekingu
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15:29
Bertl
off for a nap ... bbl
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15:29
Bertl
changed nick to: Bertl_zZ
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15:53
cbohnens
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16:08
se6astian
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16:52
se6astian|away
changed nick to: se6astian
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17:10
intracube|away
changed nick to: intracube
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19:40
slikdigit
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21:44
Bertl_zZ
changed nick to: Bertl
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21:44
Bertl
back now ...
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22:19
se6astian
time for bed
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22:19
se6astian
good night
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22:19
se6astian
changed nick to: se6astian|away
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22:26
Bertl
nn
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22:30
aombk
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22:32
aombk3
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23:31
irieger_
changed nick to: irieger
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23:50
irieger
Hey Bertl, I'm trying to understand the image pipeline of the Axiom better. Is there something that goes more in depth? Or where is the image processing code in the Github?
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23:51
irieger
Is everything after the sensor happening on the FPGA part?
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00:08
Bertl
https://wiki.apertus.org/index.php?title=Axiom_Alpha_Software
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00:08
Bertl
there is a flow chart for the image pipeline
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00:08
Bertl
the parts labeled "Fabric" are done in the FPGA
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00:09
Bertl
for the Beta, the HDMI encoder is also part of the FPGA
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00:10
Bertl
the code is on github (https://github.com/apertus-open-source-cinema/alpha-software)