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#apertus IRC Channel Logs

2019/08/01

Timezone: UTC


03:04
Fares
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Fares
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03:15
Fares
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03:20
Nira
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03:33
Fares
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05:44
BAndiT1983|away
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07:02
BAndiT1983
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07:07
Bertl_oO
off to bed now ... have a good one everyone!
07:07
Bertl_oO
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07:07
apurvanandan[m]
Good night
07:41
apurvanandan[m]
Bertl, if we want to generate a divided clock like from counter which is going to drive large number of elements, so how can we improve its routing?
08:58
Y_G_
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09:33
apurvanandan[m]
\o/
09:34
apurvanandan[m]
Bertl, I succeeded! The DDRX1 primitive worked like wonders
09:35
apurvanandan[m]
I did word alignment and 2 to 10 gearing myself using small VHDL code and now I am able to receive the counter data perfectly!
09:36
apurvanandan[m]
Here is the dump if you want to see : https://pastebin.com/g7hH33u8
09:36
apurvanandan[m]
First two columns are unnconnected, second last is the received byte from Virtex-5 and last one is generated byte in machXO2
09:37
apurvanandan[m]
And there is a constant difference of 1 between them
09:37
apurvanandan[m]
Now I will move to ber measurement :D
10:39
apurvanandan[m]
And I checked the equality of received and generated bytes on my pc using C code and for 200MBytes there wasn't any unequal value
10:40
apurvanandan[m]
Actually after that I didn't check
11:35
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Nira|away
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13:09
Bertl_zZ
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13:09
Bertl
morning folks!
13:25
Nira
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13:54
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13:55
ranga_swami
hey!! I am an open source entho!!
13:57
ranga_swami
just wanted to know, are you guys deciding to participate this year in google code in?
13:59
Bertl
hello ranga_swami!
14:00
Bertl
we haven't considered code in yet, but we are doing GSoC
14:01
ranga_swami
hey Bertl, I am in school so I can only do GCI .
14:06
Bertl
yeah, of course ...
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Nira|away
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Nira
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19:44
apurvanandan[m]
Bertl we will also need some gearing from software side on PC for 32 to 48 gearing?
19:49
BAndiT1983
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19:51
Bertl
yup
20:47
BAndiT1983|away
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21:27
Nira|away
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22:15
apurvanandan[m]
Bertl: I tried transfers at 350 MHz and 400MHz, at 350 MHz BER increased to 1.5% and at 400 MHz all data was corrupt
22:17
Bertl
so that won't work for reliable transfers
22:17
apurvanandan[m]
Yup
22:17
danieel
its 350 mbit? or x2?
22:17
apurvanandan[m]
What should I do with UDDCNTLN signal
22:17
apurvanandan[m]
x2 danieel
22:18
danieel
so 700 ~ 800.. the wire (connection) is properly made?
22:18
apurvanandan[m]
It is for PVT variation compensation, so I turn off PVT compensation when link is trained and I freeze the DLL
22:18
apurvanandan[m]
Is that the right way?
22:19
apurvanandan[m]
I used dupont cables danieel
22:20
apurvanandan[m]
Plus the machXO2 has a limit at 378 MHz
22:20
Bertl
so yes, that is a valid point, it might just be above the connection
22:20
apurvanandan[m]
Please plug USB module on remote beta Bertl
22:20
danieel
one thing would also tell a bit more - the BER is same for both directions, or one behaves much better?
22:21
apurvanandan[m]
I have implemented unidirectinal transfer only
22:21
Bertl
apurvanandan[m]: I'm pretty sure right now nobody is at the hub .. but if you provide me with bitfiles for the Beta, I can test it at home
22:22
apurvanandan[m]
I can't right now as code is for Virtex-5
22:22
apurvanandan[m]
It will take time
22:22
apurvanandan[m]
But tommorow will be fine
22:23
danieel
and the ddrx1 is used in this?
22:23
apurvanandan[m]
Yup
22:24
danieel
that is up to 300 or 250mhz only (-6 and -5) xo2 speedgrades
22:24
danieel
mbps!!
22:24
apurvanandan[m]
But later I combine words to 10 bits encoded words
22:24
danieel
*xo3
22:25
Bertl
yes, it might be interesting to see if DDR x2 can get higher rates or bails out at the same point with similar error rates
22:26
apurvanandan[m]
Ok I will try with that also
22:27
danieel
what speedgrade is the xo2?
22:30
RexOrMatrix[m]
Note: I'm not sure there's a USB module at the Hub anyways.
22:30
danieel
the XO2 supported speeds are in DS1035 page 3-19 ... and for 700mbit+ you need DDR4 and -6 part
22:31
danieel
i wonder how your design could pass timing checks :)
22:33
Bertl
RexOrMatrix[m]: there should be two, one with FT601 and one with FT602
22:33
RexOrMatrix[m]
Noted.
22:47
illwieckz
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22:55
apurvanandan[m]
I used DDR x4 earlier, but there were lot in error in the received and it was sort of blackbox, there was no way to debug word alignment by the primitive
22:55
apurvanandan[m]
@ danieel
22:56
Bertl
but you might want to check your constraints in case you didn't get any timing errors (at least for 400MHz)
22:56
Bertl
because as danieel mentioned, you should get a lot of warnings/error there
23:02
BAndiT1983
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23:05
danieel
apurvanandan[m]: these "phy" serdeses do not deal much with word alignment
23:06
danieel
its just the 4 consecutive bits, and then another 4... if you have some framing, you have to do it in logic
23:06
danieel
8b10b is only hardwired in multi-gigabit transcievers
23:07
apurvanandan[m]
I am not using transceivers
23:08
illwieckz_
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23:11
apurvanandan[m]
I am using the primitve IDDRX4B which does the word alignment using a bit slip input
23:12
illwieckz
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23:13
apurvanandan[m]
danieel: The speedgrade is -6
23:19
apurvanandan[m]
Alignment signal is ALIGNWD (mentioned in DS1035)
23:31
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23:36
apurvanandan[m]
Thanks danieel for telling about DS1035, I didn't knew that so much description was there about DDR primitives
23:37
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23:37
apurvanandan[m]
aSobhy, you should have a look over DS1035
23:41
apurvanandan[m]
Bertl, what do we do when we want to generate exact 378 MHz from 100 MHz clock by PLL?
23:42
Bertl
find a common clock rate and adjust the PLL, but I doubt that the MachXO2 PLL can do that
23:42
apurvanandan[m]
No I meant for Virtex-5
23:43
Bertl
ah, well, have to check the MMCM/PLL for the Virtex-5
23:47
apurvanandan[m]
Actually VCO freq has a limit between 400 MHz to 1GHz, and we need to multiply by 15 and divide by 4 the 100MHz clock
23:47
apurvanandan[m]
For generating 375 MHz
23:48
apurvanandan[m]
So VCO freq can't be 1.5GHHz
23:49
Bertl
got a link to the virtex 5 PLL/DCM documentation?
23:50
apurvanandan[m]
https://github.com/apurvanandan1997/Systems_Reading_Material/blob/master/XUPV5%20Virtex-5%20Documentation/ug190.pdf
23:50
apurvanandan[m]
This is the user guide
23:54
Bertl
and where does it explain the DCM?
23:55
apurvanandan[m]
From page 89
23:55
apurvanandan[m]
Chpater PLL
23:55
Bertl
ah, under PLL, tx
23:59
Bertl
so you probably need to chain two PLLs to create something in the correct range
23:59
apurvanandan[m]
:(
23:59
apurvanandan[m]
ok
00:05
apurvanandan[m]
So first multiply by 3 in first PLL, then multiply by 5 and divide by 4 in next PLL
00:05
Bertl
or 3/2 and 5/2
00:06
apurvanandan[m]
great
00:09
apurvanandan[m]
'not of locked' signal of first PLL goes to second as Reset?
00:15
Bertl
why not
00:15
apurvanandan[m]
Just comfirming
00:29
apurvanandan[m]
Should I stop the delay updation based on PVT variation when link is trained?
00:29
apurvanandan[m]
Or should I keep updating?
00:38
Bertl
PVT can change over time, so ideally you want to update continuously, not sure how well that works on the MachXO2 though
00:39
apurvanandan[m]
Ok great
00:45
apurvanandan[m]
And what about freezing DLL after link trained?