#apertus IRC Channel Logs

Bertl, if we want to generate a divided clock like from counter which is going to drive large number of elements, so how can we improve its routing?

\o/

I did word alignment and 2 to 10 gearing myself using small VHDL code and now I am able to receive the counter data perfectly!

First two columns are unnconnected, second last is the received byte from Virtex-5 and last one is generated byte in machXO2

Now I will move to ber measurement :D

Actually after that I didn't check

hey!! I am an open source entho!!

hello ranga_swami!

hey Bertl, I am in school so I can only do GCI .

Bertl: I tried transfers at 350 MHz and 400MHz, at 350 MHz BER increased to 1.5% and at 400 MHz all data was corrupt

Yup

What should I do with UDDCNTLN signal

so 700 ~ 800.. the wire (connection) is properly made?

Is that the right way?

Plus the machXO2 has a limit at 378 MHz

Please plug USB module on remote beta Bertl

I have implemented unidirectinal transfer only

I can't right now as code is for Virtex-5

But tommorow will be fine

Yup

mbps!!

*xo3

Ok I will try with that also

Note: I'm not sure there's a USB module at the Hub anyways.

i wonder how your design could pass timing checks :)

Noted.

I used DDR x4 earlier, but there were lot in error in the received and it was sort of blackbox, there was no way to debug word alignment by the primitive

but you might want to check your constraints in case you didn't get any timing errors (at least for 400MHz)

its just the 4 consecutive bits, and then another 4... if you have some framing, you have to do it in logic

I am not using transceivers

I am using the primitve IDDRX4B which does the word alignment using a bit slip input

danieel: The speedgrade is -6

Bertl, what do we do when we want to generate exact 378 MHz from 100 MHz clock by PLL?

No I meant for Virtex-5

Actually VCO freq has a limit between 400 MHz to 1GHz, and we need to multiply by 15 and divide by 4 the 100MHz clock

So VCO freq can't be 1.5GHHz

https://github.com/apurvanandan1997/Systems_Reading_Material/blob/master/XUPV5%20Virtex-5%20Documentation/ug190.pdf

and where does it explain the DCM?

Chpater PLL

so you probably need to chain two PLLs to create something in the correct range

ok

or 3/2 and 5/2

'not of locked' signal of first PLL goes to second as Reset?

Just comfirming

Or should I keep updating?

Ok great