#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

(maybe at some point, both cameras can run the same GUI?)

hi

morning folks!

do you have some time to help me

i've made a 8 bit sender (par to ser) and a 8 bits receiver (par to ser) using a pll

there are one line for data and one line for word clock

i have connected sender to receiver and i send a single pattern to view if receive one is good

but with chronogram i don't understand how the iserdes is working

the simulation :https://dl.dropboxusercontent.com/u/782577/sender_receiver_8bits.JPG

the simulation doesn't look wrong per se, it is one cycle behind

the 8 bit receiver : https://dl.dropboxusercontent.com/u/782577/receiver_8bits_clk.vhd

this is that i don't undestand

maybe i need a delay on the word bit, but i don't know why

oh in fact the word clock is uded by the iserdes to "push" the data out on the par bus right ?

clear !

you're welcome!

that is a good question, but usually data is sampled on the rising edge

ok thanks

does IDELAYE2 can be used to delayed the word clock ?

what do you mean ?

ok so i need a IDELAYE2 right ?

the one clock delay on the output is synchronous, so if you want (for whatever reason) to sync generator and receiver (not necessary) then just buffer the generator (i.e. delay it one clock)

i don't know if i have to do that by vhdl or by using a IP

what you need to do instead is to make sure that the data is either source synchronous and has some kind of word clock, or the connection is "trained" to align to a word

so you say that

it is better to send something like "17" or something like that

for example

it might mess up your first word

another solution is to use the phase of the PLL

use the phase of the pll = use a pll in the receiver with a division of 1 and change the phase

which can be used to "align" the data during "training"

the clkdiv drives the output of the serial to parallel converter, so it should be relevant

also note that the bitslip is still relevant, even if you do not use it

have you two decided if the physical need to be DC balanced (TMDS, ac-coupled) or just plain LVDS (dc-coupled) ?

probably the usable bandwith will be higher then, compared to 8/10

(dvi specifies very big tollerance to interlane skew)

can but it is not necessary

once you use an ac coupled, you cant really avoid 8/10 or tmds

and then it would be much easier just to reformat that dvi code from xilinx

Francky: ^^ is good for inspiration

8/10 makes more sense, as you can use the oob for sync/packetization

hey Lenny, yes, we are working on the web-shop

oh

cant wait to rock out to DOP rampage

\m/ ONE INCH DEPTH OF FIIIEELD, WITH MY APERTURE OPEN, ALL! THE! WAY! \m/

you can play pacman now on google streetmaps, no joke

Bertl, what do you think about my stratégy of training ? :

the receiver, which know the init pattern, use the bitslip to receive the good pattern

too complicated :)

e.g. send a coma pattern over and over again, which can be used for training

if you don't want to use a coder, make the first N patterns the sync patterns

yes, feedback is always tricky

in fact when data_in_delayed = data_out

does it seems good for you ?

when you use the PRNG, then you can drop the crosscheck

yes, but the PRNG data is generated on _both_ ends

yes i undestood that

or i just delayed the "start" of the prng

i.e. while the "idle" condition is true, the receiver PRNG is in reset

that's where the encoder comes in

(did you read the 8/10 encoding wiki entries I pasted last time?)

okay :)

yes, and some of them are very suited for synchronization

so i have a working vhdl code which can send 32 bit + clk through 5 serial lines and receive and compare to initial data, which works (on simulator)

congrats!

yep i get it and start to build it

and stat connectors

great! so you can soon test on real hardware then

but for the moment i have no coder in the transmit lines

the code make 32bits to 40 bits coding (ie 4 x 8 to 10 bits) ?

always 8/10, so you need 4 of them

?

humm in fact i think i misanderstood the way we transmit the data... in fact for each 8 bits word, i.e on each serial line, you will put a coder to build a 10 bits word and send it on the line right ?

so the iserdes/oserdes will be configurated with data lenght = 10

yup

even on low end hardware, you can use the 5bit serdes and a gearbox

would be kind of defeating the purpose, but as long as you keep the codes on one line it would actually work

if you upload a coder/decoder, i will update my sender/receiver IPs

http://vserver.13thfloor.at/Stuff/AXIOM/BETA/enc_8b10b.vhd

here you have two 8/10 bit encoders, the code is quite old so please double check it :)

do you have the decoder ?

note that decoding is rather simple if you don't care about checking for correct codes

i.e. use the "decoded" 8 bit code to generate the "correct" 10 bit code and compare it with a pipelined version of the received code

there are some undeclared signals on the 8b10b coder, but i don't know what to do with, because theyr are used once

and used only here

i.e. the encoder switches based on those signals, you can just remove the code

ciao

so, what exactly do you need in 3d modeling?

se6astian,

then we need you :)

se6astian: is there any repository of 3d mesh data for the Beta/Gamma?

https://github.com/apertus-open-source-cinema/beta-hardware/tree/master/Enclosure

for the Gamma not yet

time for bed