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#apertus IRC Channel Logs

2015/04/01

Timezone: UTC


01:13
intracube
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fsteinel
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fsteinel_
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02:25
Bertl
off to bed now ... have a good one everyone!
02:25
Bertl
changed nick to: Bertl_zZ
03:46
Jin^eLD
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07:33
alexML
this might be interesting for Apertus as well: http://www.magiclantern.fm/forum/index.php?topic=14847
07:33
alexML
(maybe at some point, both cameras can run the same GUI?)
08:21
se6astian|away
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08:38
niemand
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Francky
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08:59
Francky
hi
09:00
se6astian
good morning
09:02
Jin|away
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09:03
se6astian
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09:09
tezburma
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09:26
Bertl_zZ
changed nick to: Bertl
09:26
Bertl
morning folks!
09:27
Francky
hi Bertl
09:32
Francky
do you have some time to help me
09:32
Bertl
alexML: nice one :)
09:32
Francky
i've made a 8 bit sender (par to ser) and a 8 bits receiver (par to ser) using a pll
09:33
Bertl
Francky: ser to par I hope for the receiver :)
09:33
Francky
there are one line for data and one line for word clock
09:33
Francky
yes indeed ser to par for receiver
09:33
Francky
i have connected sender to receiver and i send a single pattern to view if receive one is good
09:34
Francky
and it is not :(
09:34
Francky
but with chronogram i don't understand how the iserdes is working
09:34
Bertl
show me the code
09:34
Francky
the simulation :https://dl.dropboxusercontent.com/u/782577/sender_receiver_8bits.JPG
09:36
Francky
the single 8 bit sender : https://dl.dropboxusercontent.com/u/782577/sender_8bits.vhd
09:36
Bertl
the simulation doesn't look wrong per se, it is one cycle behind
09:36
Francky
the 8 bit + clk sender : https://dl.dropboxusercontent.com/u/782577/sender_8bits_clk.vhd
09:36
Francky
the 8 bit receiver : https://dl.dropboxusercontent.com/u/782577/receiver_8bits_clk.vhd
09:36
Francky
yes i have one cycle that i don't know where it is :)
09:37
Francky
this is that i don't undestand
09:37
Bertl
well, there has to be a delay, the data cannot be generated and sampled instantaneously
09:37
Francky
maybe i need a delay on the word bit, but i don't know why
09:38
Bertl
it doesn't matter much, as long as you are able to sync the receiver with the word start
09:38
Francky
oh in fact the word clock is uded by the iserdes to "push" the data out on the par bus right ?
09:38
Bertl
yep
09:38
Francky
clear !
09:38
Francky
thanks
09:38
Bertl
you're welcome!
09:39
Francky
another think : how do you know if it is rising or falling edge which is used by existing IP, as iserdes for example
09:40
Bertl
that is a good question, but usually data is sampled on the rising edge
09:41
Bertl
(unless you have DDR, then there is data on both edges)
09:43
Francky
ok thanks
09:43
Bertl
np
09:48
tezburma
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tezburma
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10:10
Francky
does IDELAYE2 can be used to delayed the word clock ?
10:11
Bertl
you can delay all input to the fpga, including clock signals
10:12
Francky
what do you mean ?
10:13
Bertl
iDELAY is for inputs, ODELAY for output signals
10:14
Francky
ok so i need a IDELAYE2 right ?
10:14
Bertl
not sure what exactly you are trying to do atm?
10:15
Bertl
the one clock delay on the output is synchronous, so if you want (for whatever reason) to sync generator and receiver (not necessary) then just buffer the generator (i.e. delay it one clock)
10:15
Francky
i need to delayed the serial line "word clock" for the iserdes
10:16
Francky
i don't know if i have to do that by vhdl or by using a IP
10:17
Bertl
for the general case, i.e. transferring data over external lines, you cannot assume that kind of synchronization
10:17
Bertl
what you need to do instead is to make sure that the data is either source synchronous and has some kind of word clock, or the connection is "trained" to align to a word
10:18
Francky
i hope i undestadn right
10:18
Francky
so you say that
10:19
Francky
insteed of sending the patern "0F" for the word clock
10:19
Francky
it is better to send something like "17" or something like that
10:19
Francky
right ?
10:19
Bertl
for example
10:19
Francky
not 17 but 87
10:20
Bertl
it might mess up your first word
10:20
Bertl
but after that everything should be aligned properly
10:20
Bertl
another solution is to use the phase of the PLL
10:21
Bertl
i.e. if you generate word and bit clock with the PLL, then you can phase shift the word clock
10:21
Francky
use the phase of the pll = use a pll in the receiver with a division of 1 and change the phase
10:24
Bertl
yes, there is also the bit slip feature of the SERDES
10:24
Bertl
which can be used to "align" the data during "training"
10:37
Francky
the iserdes doesn't care about the delay of the clockdiv signal
10:53
Bertl
the clkdiv drives the output of the serial to parallel converter, so it should be relevant
10:54
Bertl
note that the simulations are often somewhat off (i.e. just models)
10:54
Bertl
also note that the bitslip is still relevant, even if you do not use it
11:03
Francky
the bitslip works
11:03
danieel
have you two decided if the physical need to be DC balanced (TMDS, ac-coupled) or just plain LVDS (dc-coupled) ?
11:08
Bertl
not yet, but I guess between FPGAs dc coupled is simpler
11:09
danieel
probably the usable bandwith will be higher then, compared to 8/10
11:09
danieel
but with tmds, or 8/10, there is a chance to recognize the pattern and tune runtime the delays on lanes - e.g. see the soft hdmi/dvi receiver core from xilinx
11:10
danieel
(dvi specifies very big tollerance to interlane skew)
11:11
Bertl
yes, but LVDS dc coupled can still use 8/10 (or TMDS) encoding
11:11
danieel
can but it is not necessary
11:11
Bertl
what I mean is, that's not a reason to use ac coupled interfaces
11:12
danieel
once you use an ac coupled, you cant really avoid 8/10 or tmds
11:12
Bertl
of course
11:12
danieel
and then it would be much easier just to reformat that dvi code from xilinx
11:13
danieel
XAPP495
11:14
danieel
Francky: ^^ is good for inspiration
11:15
Bertl
I think TMDS for inter FPGA communication is overkill
11:26
danieel
8/10 makes more sense, as you can use the oob for sync/packetization
11:29
danieel
or crate some sort of 64/66 to lower the overhead for larger packets, the scrambler could be left out as you do not need DC balance
12:03
ItsMeLenny
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12:04
ItsMeLenny
hey, theres no link to buy futile resistance, is there an online store i can buy it from
12:07
rhavan
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rhavan
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12:14
Bertl
hey Lenny, yes, we are working on the web-shop
12:14
Bertl
(so it will be available there shortly :)
12:15
ItsMeLenny
oh
12:15
ItsMeLenny
ok*
12:15
ItsMeLenny
cant wait to rock out to DOP rampage
12:16
Bertl
\m/
12:18
ItsMeLenny
\m/ ONE INCH DEPTH OF FIIIEELD, WITH MY APERTURE OPEN, ALL! THE! WAY! \m/
12:25
intracube
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12:26
ItsMeLenny
you can play pacman now on google streetmaps, no joke
12:49
Jin^eKD
changed nick to: Jin^eLD
14:27
Francky
Bertl, what do you think about my stratégy of training ? :
14:27
Francky
at start, the sender send an "init pattern"
14:27
Francky
the receiver, which know the init pattern, use the bitslip to receive the good pattern
14:28
Francky
when the pattern is good, a signal is sent to the sender to start the data flow
14:47
Bertl
too complicated :)
14:47
Bertl
for testing, the best approach is to have some kind of "idle" signal
14:48
Bertl
e.g. send a coma pattern over and over again, which can be used for training
14:48
Bertl
then, when you want to start, simply start, the receiver knows that it has started from the change in pattern
14:49
Bertl
if you don't want to use a coder, make the first N patterns the sync patterns
14:49
Bertl
where N is at least the number of steps you need to synchronize
14:53
cbohnens|away
changed nick to: cbohnens
14:55
Francky
ok so it is exactly what i mean, without the signal feedback from the receiver right ?
14:59
Bertl
yes, feedback is always tricky
15:00
Francky
ok so i add to my test program a "data_match" signal that is 1 when data_in = data_out
15:00
Francky
in fact when data_in_delayed = data_out
15:01
Francky
because i need to delayed the data_in from 3 word_clk period to take the par to ser/ser to par time
15:01
Francky
does it seems good for you ?
15:01
Francky
it is working right now
15:01
Bertl
when you use the PRNG, then you can drop the crosscheck
15:02
Francky
what do you mean by "drop the crosscheck" ? the receiver need to check if received data is matching the prng data right ?
15:03
Bertl
yes, but the PRNG data is generated on _both_ ends
15:03
se6astian|away
changed nick to: se6astian
15:04
Francky
yes i undestood that
15:05
Francky
but if generation is made at the same time at both side (sender and receiver), in the receiver time, i need to delayed the prng data to "wait" for the data from the sender
15:05
Francky
or i just delayed the "start" of the prng
15:05
Bertl
the receiver has to synchronize the PRNG with the received data
15:05
Bertl
i.e. while the "idle" condition is true, the receiver PRNG is in reset
15:06
Francky
how to be sure that the prng wil never generate the idle word ?
15:06
Bertl
that's where the encoder comes in
15:07
Bertl
i.e. if you use 8/10 bit encoding, then you have all the 256 data values plus some more, which are called commas
15:07
Bertl
(did you read the 8/10 encoding wiki entries I pasted last time?)
15:07
Francky
not totaly
15:07
niemand
left the channel
15:08
Francky
but i undestand
15:08
Bertl
okay :)
15:08
Francky
there are forbidden word due to codding which could be use as idle word
15:10
Bertl
yes, and some of them are very suited for synchronization
15:10
Francky
ok
15:38
Francky
so i have a working vhdl code which can send 32 bit + clk through 5 serial lines and receive and compare to initial data, which works (on simulator)
15:38
Francky
i'm happy :)
15:39
Bertl
congrats!
15:39
Bertl
did you get/build the breakout board yet?
15:39
Francky
yep i get it and start to build it
15:39
Francky
i mont the 100 pins connectors
15:40
Francky
and stat connectors
15:40
Francky
and pmod connectors
15:40
Bertl
great! so you can soon test on real hardware then
15:40
Francky
yes this is the next step
15:40
Francky
but for the moment i have no coder in the transmit lines
15:41
Bertl
I'll upload one
15:41
Francky
the code make 32bits to 40 bits coding (ie 4 x 8 to 10 bits) ?
15:42
Francky
coder*
15:42
Bertl
always 8/10, so you need 4 of them
15:42
Francky
ok so the output is a 40 bits word
15:42
Francky
?
15:42
Bertl
if you want to see it that way, yes
15:43
Francky
humm in fact i think i misanderstood the way we transmit the data... in fact for each 8 bits word, i.e on each serial line, you will put a coder to build a 10 bits word and send it on the line right ?
15:43
Bertl
yes, that's the idea
15:43
Francky
so the iserdes/oserdes will be configurated with data lenght = 10
15:43
Francky
is it possible ?
15:44
Bertl
yup
15:44
Francky
ok
15:44
Bertl
even on low end hardware, you can use the 5bit serdes and a gearbox
15:44
Francky
i thought it wasn't, so i imagien to make a 8/10 coding on the 32 bits word and send it throught 5 x 8 bits serial lines, which is completely idiot
15:45
Bertl
would be kind of defeating the purpose, but as long as you keep the codes on one line it would actually work
15:46
Francky
it would work BUT it is not the right way
15:46
Francky
if you upload a coder/decoder, i will update my sender/receiver IPs
15:48
Francky
does the word clock need to be coded too ?
15:48
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/enc_8b10b.vhd
15:49
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/enc_tmds.vhd
15:49
Bertl
here you have two 8/10 bit encoders, the code is quite old so please double check it :)
15:50
Francky
i will correct it :D :D
15:59
Francky
do you have the decoder ?
16:06
Bertl
I didn't code them back then, so you have to do that
16:06
Bertl
note that decoding is rather simple if you don't care about checking for correct codes
16:07
Bertl
for proper bit error checking you should also verify the codes, but that can also be done in hindsight
16:08
Bertl
i.e. use the "decoded" 8 bit code to generate the "correct" 10 bit code and compare it with a pipelined version of the received code
16:09
Francky
ok
16:10
Francky
there are some undeclared signals on the 8b10b coder, but i don't know what to do with, because theyr are used once
16:11
Francky
into the delay proc : vde, ain, ade, cin are undeclared
16:12
Francky
and used only here
16:17
Bertl
yes, that is for TMDS, which encodes video and audio
16:17
Bertl
i.e. the encoder switches based on those signals, you can just remove the code
16:18
Bertl
i.e. only the vde = '1' branch is relevant for your purpose
16:23
ItsMeLenny
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16:46
Francky
i need to go. Tomorrow i hope to put the code on the zynq and make real debug insteed of simulation :)
16:46
Francky
ciao
16:46
Bertl
cya!
16:47
Francky
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17:03
Jin^eLD
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jucar
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cbohnens
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intracube
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se6astian
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niemand
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19:00
se6astian|away
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intracube
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20:04
aombk
so, what exactly do you need in 3d modeling?
20:11
g3gg0
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niemand
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20:31
se6astian
aombk: you mean I can make a wish? :)
21:08
tezburma
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21:37
aombk
i mean i do 3d modeling and visualization and i saw something in one email. but i though you were covered in 3d modeling and visualization etc
21:37
aombk
se6astian,
22:12
se6astian
ha
22:13
se6astian
then we need you :)
22:13
se6astian
we need illustrations and visualizations for the Beta and the Gamma
22:27
intracube
se6astian: is there any repository of 3d mesh data for the Beta/Gamma?
22:29
niemand
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23:15
intracube
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23:15
se6astian
yes
23:15
se6astian
https://github.com/apertus-open-source-cinema/beta-hardware/tree/master/Enclosure
23:15
se6astian
everything Beta related
23:15
se6astian
for the Gamma not yet
23:16
se6astian
its all concept art for now
23:29
se6astian
time for bed
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cfelton
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se6astian
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Andrej741
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